The audio converters in the TLV320AIC3104-Q1 need an internal audio master clock at a frequency of 256 fS(ref), which can be obtained in a variety of manners from an external clock signal applied to the device.

A more detailed diagram of the audio clock section of the TLV320AIC3104-Q1 is shown in Figure 7-21.

Figure 7-21 Audio Clock Generation Processing

The device can accept an MCLK input from 512 kHz to 50 MHz that can then be passed through either a programmable divider or a PLL to get the proper internal audio master clock required by the device. The BCLK input can also be used to generate the internal audio master clock.

A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies available in the system. This device includes a highly programmable PLL to accommodate such situations easily. The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus paid to the standard MCLK rates already widely used.

When the PLL is disabled,

where

• Q = {2 to 17}. Q is register programmable and can be set in page 0, register 3, bits D6 to D3
• CLKDIV_IN can be MCLK or BCLK, selected by register 102, bits D7 to D6

When the PLL is enabled,

where

• P = {1 to 8}
• R = {1 to 16}
• K = J.D
• J = {1 to 63}
• D = {0000 to 9999}
• PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5 to D4

P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision). P can be set in page 0, register 3, bits D2 to D0. R can be set in page 0, register 11, bits D3 to D0. J can be set in page 0, register 4, bits D7 to D2. The most-significant bits of D can be set in page 0, register 5, bits D7 to D0, and the least-significant bits of D can be set in page 0, register 6, bits D7 to D2.

Examples:

If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified performance:

2 MHz ≤ (PLLCLK_IN / P) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R / P) ≤ 110 MHz
4 ≤ J ≤ 55

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified performance:

10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4 ≤ J ≤ 11
R = 1

Example:

MCLK = 12 MHz and f_S(ref) = 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example:

MCLK = 12 MHz and f_S(ref) = 48 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Table 7-5 lists several example cases of typical MCLK rates and how to program the PLL to achieve f_S(ref) = 44.1 kHz or 48 kHz.