8.3.2.1 Audio Serial Interface

The audio interface port is a 3-wire serial port with the signals LRCK, BCK, and DIN. BCK is the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the audio interface. Serial data is clocked into the PCM514x on the rising edge of BCK. LRCK is the serial audio left/right word clock. LRCK polarity for left/right is given by the format selected.

The PCM514x requires the synchronization of LRCK and system clock, but does not need a specific phase relation between LRCK and system clock.

If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation (using an onchip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock is completed.

If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation (using an onchip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and BCK is completed.

8.3.2.2 PCM Audio Data Formats

The PCM514x supports industry-standard audio data formats, including standard I²S and left-justified. Data formats are selected via Register (Pg0Reg40). All formats require binary twos-complement, MSB-first audio data; up to 32-bit audio data is accepted.

The PCM514x also supports right-justified and TDM/DSP in software control mode. I²S, LJ, RJ, and TDM/DSP are selected using Register (Pg0Reg40). All formats require binary twos-complement, MSB-first audio data. Up to 32 bits are accepted. Default setting is I²S and 24-bit word length.

The following data formats are only available in software mode.

NOTE

In TDM Modes, Duty Cycle of LRCK should be 1x BCK at minimum. Rising edge is considered frame start.

8.3.2.3 Zero Data Detect

The PCM514x has a zero-detect function. When the device detects the continuous zero data for both left and right channels, or separate channels, Analog mutes are set to both OUTL and OUTR, or separate OUTL and OUTR. These are controlled by Page 0, Register 65, D(2:1) as shown in Table 5.

Continuous Zero data cycles are counted by LRCK, and the threshold of decision for analog mute can be set by Page 0, Register 59, D(6:4) for L-ch, and D(2:0) for Rch as shown in Table 6. Default values are 0 for both channels.

In Hardware mode, the device uses default values. By default, Both L-ch and R-ch have to be zero data for zero data detection to begin the muting process etc.

8.3.4.1 PCM514x Audio Processing Options

8.3.4.2 Interpolation Filter

The PCM514x provides 4 types of interpolation filters, selectable by writing to Page 0, Register 43, D(4:0).

Additional RAM based Hybrid Flows can be implemented by selecting Program 31, and downloading instructions and coefficients to the device.

The PCM514x supports four sampling modes (single rate, dual rate, quad rate, and octal rate) which produce different oversampling rates (OSR) in the interpolation digital filter operation. These are shown in Table 8.

SPACE

SPACE

SPACE

SPACE

SPACE

SPACE

SPACE

SPACE

SPACE

SPACE

SPACE

SPACE

8.3.4.3 Fixed Audio Processing Flow (Program 5)

The PCM514x implements signal processing capabilities and interpolation filtering via processing blocks. These fixed processing blocks give users the choice of how much and what type of signal processing they may use and which interpolation filter is applied.

The signal processing blocks available are:

• Biquad filters
• Multiband DRC
• Mono mixer
• Stereo mixer
• Master volume

The addresses of the coefficients are fixed when selecting the fixed processing flow, however, if these components are used in the RAM source mode (Program 31) the registers for coefficients will change. Users can find more details in Purepath Studio.

NOTE

This process flow requires 1024 instruction cycles. Therefore, it will only function at sampling frequencies up to 48 kHz.

8.3.5.1 Analog Outputs

The PCM514x devices include a two-channel DAC, with single-ended outputs. The full-scale output voltage is 2.1V_rms with ground center output. A dc-coupled load is supported in addition to an ac-coupled load, if the load resistance conforms to the specification. The PCM514x DAC outputs on the OUTL and OUTR terminals have market-leading low out-of-band noise, which offer up to 20dB lower out-of-band noise compared with existing DAC technology.

Most applications require an external low-pass RC filter (470Ω + 2.2nF) to provide sufficient out-of-band noise rejection. This RC filter provides the added advantage of improved protection against ESD damage.

8.3.5.2 Recommended Output Filter for the PCM514x

The diagram in Figure 63 shows the recommended output filter for the PCM514x. The new PCM514x next-generation current segment architecture offers excellent out-of-band noise, making a traditional 20-kHz low pass filter a thing of the past.

The RC settings below offer a –3-dB filter point at 153 kHz (approximately), giving the DAC the ability to reproduce virtually all frequencies through to it’s maximum sampling rate of 384 kHz. A NP0/C0G type capacitor is strongly recommended for the shunt capacitor for lowest distortion.

8.3.5.3 Choosing Between VREF and VCOM Modes

VREF mode is the default configuration. This mode allows full 2.1-V_rms signal output. As shown in Recommended Operating Conditions, the minimum AVDD to avoid clipping is 3.2 V.

VCOM mode allows setting a custom common-mode voltage when required by the application. This somewhat limits the output signal swing before clipping.

8.3.5.4 Digital Volume Control

A basic digital volume control with range from 24 dB to –103 dB and mute is available on each channels by Page 0, Resister 61, D(7:0) for L-ch and Register 62, D(7:0) for R-ch. These volume controls all have 0.5-dB step programmability over most gain and attenuation ranges. Table 29 lists the detailed gain versus programmed setting for this basic volume control. Volume can be changed for both L-ch and R-ch at the same time or independently by Page 0, Register 60, D(1:0). When D(1:0) set 00 (default), independent control is selected. When D(1:0) set 01, R-ch accords with L-ch volume. When D(1:0) set 10, L-ch accords with R-ch volume. To set D(1:0) to 11 is prohibited.

NOTE

This volume control is done externally to the miniDSP and only influences the analog DAC output. Any changes to the SDOUT data should be done in the miniDSP process flow.

Ramp-up frequency and ramp-down frequency can be controlled by Page 0, Register 63, D(7:6) and D(3:2) as shown in Table 30. Also Ramp-up step and ramp-down step can be controlled by Page 0, Register 63 D(5:4) and D(1:0) as shown in Table 31.

8.3.5.5 Analog Gain Control

Analog gain control can be selected between 2-V_rms FS (0dB) or 1-V_rms FS (–6 dB). Gain is controlled through hardware by the AGNS pin, and through software (SPI/I²C), Page 1, Register 2, D4(L-ch) / D0(R-ch).

8.3.6.1 Clocking Overview

The PCM514x devices have flexible systems for clocking. Internally, the device requires a number of clocks, mostly at related clock rates to function correctly. All of these clocks can be derived from the serial audio interface in one form or another.

As shown in Figure 64 the data flows at the sample rate (f_S). Once the data is brought into the serial audio interface, it gets processed, interpolated and modulated all the way to 128 × f_S before arriving at the current segments for the final digital to analog conversion.

The clock tree is shown in Figure 65.

The serial audio interface typically has 4 connections: SCK (system master clock), BCK (bit clock), LRCK (left right word clock), and DIN (data). The device has an internal PLL that is used to take either SCK or BCK and create the higher rate clocks required by the interpolating processor and the DAC clock. This allows the device to operate with or without an external SCK.

In situations where the highest audio performance is required, it is suggested that the SCK is brought to the device, along with BCK and LRCK. The device should be configured so that the PLL is only providing a clock source to the miniDSP. By ensuring that the DACCK (DAC Clock) is being driven by the external SCK source, jitter evident in the PLL (in all PLLs) is kept out of the DAC, charge pump, and oversampling system.

Everything else should be a division of the incoming SCK. This is done by setting DAC CLK Source Mux (SDAC in Figure 65) to use SCK as a source, rather than the output of the SCK/PLL Mux. Code examples for this are available in SLASE12.

When the Auto Clock Configuration bit is set (Page 0/ Register 0x25), no additional clocks configuration is required. However, when setting custom PLL values and so forth, the target output rates should match those shown in the recommended PLL values of Table 132.

8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I²S)

The PCM514x requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input and supports up to 50 MHz. The PCM514x system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies in the bands of 8 kHz, 16 kHz, (32 kHz - 44.1 kHz - 48 kHz), (88.2kHz - 96kHz), (176.4 kHz - 192 kHz), and 384 kHz with ±4% tolerance are supported. Values in the parentheses are grouped when detected, (for example, 88.2 kHZ and 96 kHz are detected as double rate, and 32 kHz, 44.1 kHz and 48 kHz are detected as single rate.)

In the presence of a valid bit SCK, BCK and LRCK in software mode, the device will auto-configure the clock tree and PLL to drive the miniDSP as required.

The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge Pump (NCP) automatically. Table 32 shows examples of system clock frequencies for common audio sampling rates.

SCK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are only supported in software mode by configuring various PLL and clock-divider registers. This programmability allows the device to become a clock master and drive the host serial port with LRCK and BCK, from a non-audio related clock (for example, using 12 MHz to generate 44.1 kHz [LRCK] and 2.8224 MHz [BCK]).

See Timing Requirements: PCM Audio Data for clock timing requirements.

8.3.6.3 Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)

The system clock PLL mode allows designers to use a simple 3-wire I²S audio source. The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency electromagnetic interference.

In hardwired mode, the internal PLL is disabled as soon as an external SCK is supplied.

In hardwired mode, the device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal SCK from the BCK reference. Specific BCK rates are required to generate an appropriate master clock. Table 33 describes the minimum and maximum BCK per LRCK for the integrated PLL to automatically generate an internal SCK.

In software mode, the user must set all the PLL registers and clock divider registers for referencing BCK. See Clock Generation Using the PLL for more information. Recommended values can be found in Table 132.

8.3.6.4 Clock Generation Using the PLL

The PCM514x supports a wide range of options to generate the required clocks for the DAC section as well as interface and other control blocks as shown in Figure 65.

The clocks for the PLL require a source reference clock. This clock is sourced as the incoming BCK or SCK. In software mode, a GPIO can also be used.

The source reference clock for the PLL reference clock is selected by programming the SRCREF value on Page 0, Register 13, D(6:4). The PCM514x provides several programmable clock dividers to achieve a variety of sampling rates for the DAC and clocks for the NCP, OSR, and the miniDSP. OSRCK for OSR must be set at 16 f_S frequency by DOSR on Page0, Register 30, D(6:0). See Figure 65.

If PLL functionality is not required, set the PLLEN value on Page 0, Register 4, D(0) to 0. In this situation, an external SCK is required.

8.3.6.5 PLL Calculation

The PCM514x has an on-chip PLL with fractional multiplication to generate the clock frequency needed by the audio DAC, Negative Charge Pump, Modulator and Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input (PLLCKIN) supports clock frequencies from 1 MHz to 50 MHz and is register programmable to enable generation of required sampling rates with fine precision.

The PLL is enabled by default. The PLL can be turned on by writing to Page 0, Register 4, D(0). When the PLL is enabled, the PLL output clock PLLCK is given by Equation 3.

R, J, D, and P are programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

8.3.6.6 Clock Master Mode from Audio Rate Master Clock

In Master Mode, the device generates bit clock (BCK) and left-right clock (LRCK) and outputs them on the appropriate pins. To configure the device in this mode, first put the device into reset, then use registers BCKO and LRKO (Pg 0, Reg 9 0x09). Then reset the LRCK and BCK divider counters using bits RBCK and RLRK (Pg 0, Reg 12 0x0C). Finally, exit reset.

An example of this is given in register programming examples in the PCM5242 data sheet (SLASE12.)

Figure 66 shows a simplified serial port clock tree for the device in master mode.

In master mode, SCK is an input and BCK/LRCK are outputs. BCK and LRCK are integer divisions of SCK. Master mode with a non-audio rate master clock source will require external GPIOs to use the PLL in standalone mode.

The PLL will also need to be configured to ensure that the onchip miniDSP processor can be driven at its maximum clock rate.

Register changes that need to be done include switching the device into master mode, and setting the divider ratio.

Here is an example of using 24.576 MCLK as a master clock source and driving the BCK and LRCK with integer dividers to create 48 kHz.

In this mode, the DAC section of the device is also running from the PLL output. While the PLL inside the PCM514x is one that has been specified to achieve the stated performance, using the SCK CMOS Oscillator source will have less jitter.

To switch the DAC clocks (SDAC in the Figure 65) the following registers should be modified.

• Clock Tree Flex Mode (Page 253, Registers 0x3F and 0x40)
• DAC and OSR Source Clock Register (Page 0, Reg 14) – set to 0x30 (SCK input, and OSR is set to whatever the DAC source is)
• The DAC clock divider should be 16 F_S.
  • 16 × 48 kHz = 768 kHz
  • 24.576 MHz (SCK in) / 768 kHz = 32
  • Therefor, divide ratio for register DDAC (Page 0, Reg 28 0x1C) should be set to 32. The may the register is mapped gives 0x00 = 1, so 32 must be converted to 0x1F.

An example configuration can be found in the PCM5242 data sheet (SLASE12).

8.3.6.7 Clock Master from a Non-Audio Rate Master Clock

The classic example here is running a 12-MHz Master clock for a 48-kHz sampling system. Given the clock tree for the device (shown in Figure 65), a non-audio clock rate cannot be brought into the SCK to the PLL in master mode. Therefore, the PLL source must be configured to be a GPIO pin, and the output brought back into another GPIO pin.

The clock flow through the system is shown in Figure 67. The newly-generated SCK must be brought out of the device on a GPIO pin, then brought into the SCK pin for integer division to create BCK and LRCK outputs.

NOTE

Pullup resistors must be used on BCK and LRCK in this mode to ensure the device does not go into sleep mode.

A code example for configuring this mode is provided in the PCM5242 data sheet (SLASE12).

8.4.1.1 Software Control