SLAS831D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
PLLs can be used in all modes to generate the clocks required to run both fixed-function DSPs. The dividers are automatically configured based on the clock rate detection. The clock architecture shown in Figure 33 allows non-audio clock sources to be used as clock sources and the PCM186x to continue to run in a master mode, providing all PCM and I2S clocks for other converters in the system.
Target Clock Rates for the ADC, DSP1 and DSP2 can be seen in Table 9 and Table 10. In manual clock configuration modes, the dividers should be set to achieve these targets. In short, for 2-channel devices, DSP1 and DSP2 should be 256x the sampling rate; for 4-channel devices, DSP1 should be configured for 512x the sampling rate, and DSP2 should be 256x.