SLAS831D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VINL2/VIN1M | Analog input | Analog input 2, L-channel (or differential M input for input 1) |
2 | VINR2/VIN2M | Analog input | Analog input 2, R-channel (or differential M input for input 2) |
3 | VINL1/VIN1P | Analog input | Analog input 1, L-channel (or differential P input for input 1) |
4 | VINR1/VIN2P | Analog input | Analog input 1, R-channel (or differential P input for input 2) |
5 | Mic Bias | Power | Microphone bias output |
6 | VREF | Power | Reference voltage output decoupling point (typically, 0.5 AVDD). Connect 1-µF capacitor from this pin to AGND. |
7 | AGND | Power | Analog ground |
8 | AVDD | Power | Analog power supply (typically, 3.3 V). Connect 0.1-µF and 10-µF capacitors from this pin to AGND. |
9 | XO | Digital output | Crystal oscillator output |
10 | XI | Digital input | Crystal oscillator input or master clock input (1.8-V CMOS signal) |
11 | LDO | Power | Internal low-dropout regulator (LDO) decoupling output, or external 1.8-V input to bypass LDO. Connect 0.1-µF and 10-µF capacitors from this pin to DGND. |
12 | DGND | Power | Digital ground |
13 | DVDD | Power | Digital power supply (typically, 3.3 V). Connect 0.1-µF and 10-µF capacitors from this pin to DGND. |
14 | IOVDD | Power | Power supply for I/O voltages (typically, 3.3 V or 1.8 V). |
15 | SCKI | Digital input | CMOS level (3.3 V) master clock input |
16 | LRCK | Digital input/output | Audio data word clock (left right clock) input/output(1) |
17 | BCK | Digital input/output | Audio data bit clock input/output(1) |
18 | DOUT | Digital output | Audio data digital output |
19 | INT | Analog output | Interrupt output (for analog input detection). Pull high for active mode, pull low for idle. |
20 | MD6 | Analog input | Analog MUX and gain selection using MD6, MD5, and MD2 pins, respectively:
000: SE Ch 1 (VINL1 and VINR1) 001: SE Ch 2 (VINL2 and VINR2) 010: SE Ch 3 (VINL3 and VINR3) 011: SE Ch 4 (VINL4 and VINR4) 100: SE Ch 4 with 12-dB gain 101: SE Ch 4 with 32-dB gain 110: Diff Ch 1 (VIN1P and VIN1M, VIN2P and VIN2M) 111: Diff Ch 2 (VIN3P and VIN3M, VIN4P and VIN4M) with 12-dB gain |
21 | MD5 | Analog input | Analog MUX and gain selection (see MD6 pin for description) |
22 | MD4 | Analog input | Audio format: high = left-justified, low = I2S |
23 | MD2 | Analog input | Analog MUX and gain selection (see MD6 pin for description) |
24 | MD3 | Digital Input | Filter select: 0 = FIR decimation filter, 1 = IIR low latency decimation filter |
25 | MD1 | Analog input | Audio interface mode selection using MD1 and MD0 pins, respectively:
00: Slave mode, 256 × fS, 384 × fS, 512 × fS autodetect 01: Master mode (512 × fS) 10: Master mode (384 × fS) 11: Master mode (256 × fS) |
26 | MD0 | Analog input | Audio interface mode selection (see MD1 pin for description) |
27 | VINL4/VIN4M | Analog input | Analog input 4, L-channel (or differential M input for input 4) |
28 | VINR4/VIN3M | Analog input | Analog input 4, R-channel (or differential M input for input 3) |
29 | VINL3/VIN4P | Analog input | Analog input 3, L-channel (or differential P input for input 4) |
30 | VINR3/VIN3P | Analog input | Analog input 3, R-channel (or differential P input for input 3) |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VINL2/VIN1M | Analog input | Analog input 2, L-channel (or differential M input for input 1) |
2 | VINR2/VIN2M | Analog input | Analog input 2, R-channel (or differential M input for input 2) |
3 | VINL1/VIN1P | Analog input | Analog input 1, L-channel (or differential P input for input 1) |
4 | VINR1/VIN2P | Analog input | Analog input 1, R-channel (or differential P input for input 2) |
5 | Mic Bias | Power | Microphone bias output |
6 | VREF | Power | Reference voltage output decoupling point (typically, 0.5 AVDD). Connect 1-µF capacitor from this pin to AGND. |
7 | AGND | Power | Analog ground |
8 | AVDD | Power | Analog power supply (typically, 3.3 V). Connect 0.1-µF and 10-µF capacitors from this pin to AGND. |
9 | XO | Digital output | Crystal oscillator output |
10 | XI | Digital input | Crystal oscillator input or master clock input (1.8-V CMOS signal) |
11 | LDO | Power | Internal LDO decoupling output, or external 1.8-V input to bypass LDO. Connect 0.1-µF and 10-µF capacitors from this pin to DGND. |
12 | DGND | Power | Digital ground |
13 | DVDD | Power | Digital power supply (typically, 3.3 V). Connect 0.1-µF and 10-µF capacitors from this pin to DGND. |
14 | IOVDD | Power | Power supply for I/O voltages (typically, 3.3 V or 1.8 V). |
15 | SCKI | Digital input | CMOS level (3.3 V) master clock input |
16 | LRCK | Digital input/output | Audio data world clock (left right clock) input/output(1) |
17 | BCK | Digital input/output | Audio data bit clock input/output(1) |
18 | DOUT | Analog output | Audio data digital output |
19 | GPIO3/INTC | Digital input/output | GPIO 3 or interrupt C |
20 | GPIO2/INTB/DMCLK | Digital input/output | GPIO 2, interrupt B, or digital microphone clock output |
21 | GPIO1/INTA/DMIN | Digital input/output | GPIO 1, interrupt A, or digital microphone input |
22 | MISO/GPIO0/DMIN2 | Digital input/output | In SPI mode: master in, slave out
In I2C mode: GPIO0 (or DMIN2 for PCM1864 and PCM1865 only) |
23 | MOSI/SDA | Digital input/output | In SPI mode: master out, slave in
In I2C mode: SDA |
24 | MC/SCL | Digital input | In SPI mode: serial bit clock
In I2C mode: serial bit clock |
25 | MS/AD | Digital input | In SPI mode: chip select
In I2C mode: address pin |
26 | MD0 | Digital input | Control method select pin: I2C (tied low or not connected) or SPI (tied high) |
27 | VINL4/VIN4M | Analog input | Analog input 4, L-channel (or differential M input for input 4) |
28 | VINR4/VIN3M | Analog input | Analog input 4, R-channel (or differential M input for input 3) |
29 | VINL3/VIN4P | Analog input | Analog input 3, L-channel (or differential P input for input 4) |
30 | VINR3/VIN3P | Analog input | Analog input 3, R-channel (or differential P input for input 3) |