SLASE59F
October 2015 – December 2019
MSP430FR2433
PRODUCTION DATA.
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Device Comparison
3.1
Related Products
4
Terminal Configuration and Functions
4.1
Pin Diagram
4.2
Pin Attributes
4.3
Signal Descriptions
4.4
Pin Multiplexing
4.5
Buffer Types
4.6
Connection of Unused Pins
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Active Mode Supply Current Into VCC Excluding External Current
5.5
Active Mode Supply Current Per MHz
5.6
Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
5.7
Low-Power Mode (LPM3 and LPM4) Supply Currents (Into VCC) Excluding External Current
5.8
Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
5.9
Typical Characteristics - Low-Power Mode Supply Currents
Table 5-1
Typical Characteristics – Current Consumption Per Module
5.10
Thermal Resistance Characteristics
5.11
Timing and Switching Characteristics
5.11.1
Power Supply Sequencing
Table 5-2
PMM, SVS and BOR
5.11.2
Reset Timing
Table 5-3
Wake-up Times From Low-Power Modes and Reset
5.11.3
Clock Specifications
Table 5-4
XT1 Crystal Oscillator (Low Frequency)
Table 5-5
DCO FLL, Frequency
Table 5-6
DCO Frequency
Table 5-7
REFO
Table 5-8
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
Table 5-9
Module Oscillator (MODOSC)
5.11.4
Digital I/Os
Table 5-10
Digital Inputs
Table 5-11
Digital Outputs
5.11.4.1
Typical Characteristics – Outputs at 3 V and 2 V
5.11.5
VREF+ Built-in Reference
Table 5-12
VREF+
5.11.6
Timer_A
Table 5-13
Timer_A
5.11.7
eUSCI
Table 5-14
eUSCI (UART Mode) Clock Frequency
Table 5-15
eUSCI (UART Mode)
Table 5-16
eUSCI (SPI Master Mode) Clock Frequency
Table 5-17
eUSCI (SPI Master Mode)
Table 5-18
eUSCI (SPI Slave Mode)
Table 5-19
eUSCI (I2C Mode)
5.11.8
ADC
Table 5-20
ADC, Power Supply and Input Range Conditions
Table 5-21
ADC, 10-Bit Timing Parameters
Table 5-22
ADC, 10-Bit Linearity Parameters
5.11.9
FRAM
Table 5-23
FRAM
5.11.10
Debug and Emulation
Table 5-24
JTAG, Spy-Bi-Wire Interface
Table 5-25
JTAG, 4-Wire Interface
6
Detailed Description
6.1
Overview
6.2
CPU
6.3
Operating Modes
6.4
Interrupt Vector Addresses
6.5
Bootloader (BSL)
6.6
JTAG Standard Interface
6.7
Spy-Bi-Wire Interface (SBW)
6.8
FRAM
6.9
Memory Protection
6.10
Peripherals
6.10.1
Power-Management Module (PMM)
6.10.2
Clock System (CS) and Clock Distribution
6.10.3
General-Purpose Input/Output Port (I/O)
6.10.4
Watchdog Timer (WDT)
6.10.5
System (SYS) Module
6.10.6
Cyclic Redundancy Check (CRC)
6.10.7
Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
6.10.8
Timers (Timer0_A3, Timer1_A3, Timer2_A2 and Timer3_A2)
6.10.9
Hardware Multiplier (MPY)
6.10.10
Backup Memory (BAKMEM)
6.10.11
Real-Time Clock (RTC)
6.10.12
10-Bit Analog-to-Digital Converter (ADC)
6.10.13
Embedded Emulation Module (EEM)
6.11
Input/Output Diagrams
6.11.1
Port P1 Input/Output With Schmitt Trigger
6.11.2
Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
6.11.3
Port P2 (P2.3 to P2.7) Input/Output With Schmitt Trigger
6.11.4
Port P3 (P3.0 to P3.2) Input/Output With Schmitt Trigger
6.12
Device Descriptors
6.13
Memory
6.13.1
Memory Organization
6.13.2
Peripheral File Map
6.14
Identification
6.14.1
Revision Identification
6.14.2
Device Identification
6.14.3
JTAG Identification
7
Applications, Implementation, and Layout
7.1
Device Connection and Layout Fundamentals
7.1.1
Power Supply Decoupling and Bulk Capacitors
7.1.2
External Oscillator
7.1.3
JTAG
7.1.4
Reset
7.1.5
Unused Pins
7.1.6
General Layout Recommendations
7.1.7
Do's and Don'ts
7.2
Peripheral- and Interface-Specific Design Information
7.2.1
ADC Peripheral
7.2.1.1
Partial Schematic
7.2.1.2
Design Requirements
7.2.1.3
Layout Guidelines
8
Device and Documentation Support
8.1
Getting Started and Next Steps
8.2
Device Nomenclature
8.3
Tools and Software
8.4
Documentation Support
8.5
Community Resources
8.6
Trademarks
8.7
Electrostatic Discharge Caution
8.8
Export Control Notice
8.9
Glossary
9
Mechanical, Packaging, and Orderable Information
6
Detailed Description