SLASEE2
February 2018
DAC8771
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
DAC8771 Block Diagram
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements: Write and Readback Mode
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Current Output Stage
8.3.2
Voltage Output Stage
8.3.3
Buck-Boost Converter
8.3.3.1
Buck-Boost Converter Outputs
8.3.3.2
Selecting and Enabling Buck-Boost Converter
8.3.3.3
Configurable Clamp Feature and Current Output Settling Time
8.3.3.3.1
Default Mode - CCLP[1:0] = "00"
8.3.3.3.2
Fixed Clamp Mode - CCLP[1:0] = "01"
8.3.3.3.3
Auto Learn Mode - CCLP[1:0] = "10"
8.3.3.3.4
High Side Clamp (HSCLMP)
8.3.4
Analog Power Supply
8.3.5
Digital Power Supply
8.3.6
Internal Reference
8.3.7
Power-On-Reset
8.3.8
ALARM Pin
8.3.9
Power GOOD bit
8.3.10
Status Register
8.3.11
Status Mask
8.3.12
Alarm Action
8.3.13
Watchdog Timer
8.3.14
Programmable Slew Rate
8.3.15
HART Interface
8.4
Device Functional Modes
8.4.1
Serial Peripheral Interface (SPI)
8.4.1.1
Stand-Alone Operation
8.4.1.2
Daisy-Chain Operation
8.4.2
SPI Shift Register
8.4.3
Write Operation
8.4.4
Read Operation
8.4.5
Updating the DAC Outputs and LDAC Pin
8.4.5.1
Asynchronous Mode
8.4.5.2
Synchronous Mode
8.4.6
Hardware RESET Pin
8.4.7
Hardware CLR Pin
8.4.8
Frame Error Checking
8.4.9
DAC Data Calibration
8.4.9.1
DAC Data Gain and Offset Calibration Registers
8.5
Register Maps
8.5.1
Register Maps
8.5.1.1
DAC8771 Commands
8.5.1.2
Register Maps and Bit Functions
8.5.1.2.1
No Operation Register (address = 0x00) [reset = 0x0000]
Table 6.
No Operation Field Descriptions
8.5.1.2.2
Reset Register (address = 0x01) [reset = 0x0000]
Table 7.
Reset Register Field Descriptions
8.5.1.2.3
Reset Config Register (address = 0x02) [reset = 0x0000]
Table 8.
Reset Config Register Field Descriptions
8.5.1.2.4
Select DAC Register (address = 0x03) [reset = 0x0000]
Table 9.
Select DAC Register Field Descriptions
8.5.1.2.5
Configuration DAC Register (address = 0x04) [reset = 0x0000]
Table 10.
Configuration DAC Register Field Descriptions
8.5.1.2.6
DAC Data Register (address = 0x05) [reset = 0x0000]
Table 11.
DAC Data Register Field Descriptions
8.5.1.2.7
Select Buck-Boost Converter Register (address = 0x06) [reset = 0x0000]
Table 12.
Select Buck-Boost Converter Register Field Descriptions
8.5.1.2.8
Configuration Buck-Boost Register (address = 0x07) [reset = 0x0000]
Table 13.
Configuration Buck-Boost Register Field Descriptions
8.5.1.2.9
DAC Channel Calibration Enable Register (address = 0x08) [reset = 0x0000]
Table 14.
DAC Channel Calibration Enable Register Field Descriptions
8.5.1.2.10
DAC Channel Gain Calibration Register (address = 0x09) [reset = 0x0000]
Table 15.
DAC Channel Gain Calibration Register Field Descriptions
8.5.1.2.11
DAC Channel Offset Calibration Register (address = 0x0A) [reset = 0x0000]
Table 16.
DAC Channel Offset Calibration Register Field Descriptions
8.5.1.2.12
Status Register (address = 0x0B) [reset = 0x1000]
Table 17.
Status Register Field Descriptions
8.5.1.2.13
Status Mask Register (address = 0x0C) [reset = 0x0000]
Table 18.
Status Mask Register Field Descriptions
8.5.1.2.14
Alarm Action Register (address = 0x0D) [reset = 0x0000]
Table 19.
Alarm Action Register Field Descriptions
8.5.1.2.15
User Alarm Code Register (address = 0x0E) [reset = 0x0000]
Table 20.
User Alarm Code Register Field Descriptions
8.5.1.2.16
Reserved Register (address = 0x0F) [reset = N/A]
Table 21.
Reserved Register Field Descriptions
8.5.1.2.17
Write Watchdog Timer Register (address = 0x10) [reset = 0x0000]
Table 22.
Write Watchdog Timer Register Field Descriptions
8.5.1.2.18
Reserved Register (address 0x12 - 0xFF) [reset = N/A]
Table 23.
Reserved Register Field Descriptions
9
Application and Implementation
9.1
Application Information
9.1.1
Buck-Boost Converter External Component Selection
9.1.2
Voltage and Current Outputs on a Shared Terminal
9.1.3
Optimizing Current Output Settling Time with Auto-Learn Mode
9.1.4
Protection for Industrial Transients
9.1.5
Implementing HART with DAC8771
9.2
Typical Application
9.2.1
Single-Channel, Isolated, EMC and EMI Protected Analog Output Module with Adaptive Power Management
9.2.2
Design Requirements
9.2.3
Detailed Design Procedure
9.2.4
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Third-Party Products Disclaimer
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Receiving Notification of Documentation Updates
12.4
Community Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Mechanical, Packaging, and Orderable Information
9.2.4
Application Curves
Figure 127.
Voltage Output TUE
Figure 128.
Current Output TUE