8.4.1.2 Daisy-Chain Operation

For systems that contain more than one device, the SDO pin can be used to daisy-chain multiple devices together. Daisy-chain operation can be useful for system diagnostics and in reducing the number of serial interface lines. The daisy chain feature can be enabled by writing logic '0' to DSDO bit address 0x03 (), the SDO pin is set to HiZ when DSDO bit is set to 1. By connecting the SDO of the first device to the SDIN input of the next device in the chain, a multiple-device interface is constructed, as Figure 102 illustrates.

The DAC8771 provides two modes for daisy-chain operation: normal and transparent. The TRN bit in the Reset config register determines which mode is used. In Normal mode (TRN bit = '0'), the data clocked into the SDIN pin are transferred into the shift register. The first falling edge of SYNC starts the operating cycle. SCLK is continuously applied to the SPI Shift Register when SYNC is low. If more than 24 clock pulses are applied, the data ripple out of the shift register and appear on the SDO line. These data are clocked out on the rising edge of SCLK and are valid on the falling edge. By connecting the SDO pin of the first device to the SDIN input of the next device in the chain, a multiple-device interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of DAC8771s in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This action latches the data from the SPI Shift registers to the device internal registers synchronously for each device in the daisy-chain, and prevents any further data from being clocked in. Note that a continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. For gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock in order to latch the data.

In Transparent mode (address 0x02h, TRN bit = '1' Table 5), the data clocked into SDIN are routed to the SDO pin directly; the Shift Register is bypassed. When SCLK is continuously applied with SYNC low, the data clocked into the SDIN pin appear on the SDO pin almost immediately (with approximately a 12 ns delay); there is no 24 clock delay, as there is in normal operating mode. While in Transparent mode, no data bits are clocked into the Shift Register, and the device does not receive any new data or commands. Putting the device into transparent mode eliminates the 24 clock delay from SDIN to SDO caused by the Shift Register, thus greatly speeding up the data transfer. For example, consider three DAC8771s (C, B, and A) in a daisy-chain configuration (Figure 102). The data from the SPI controller are transferred first to C, then to B, and finally to A. In normal daisy-chain operation, a total of 72 clocks are needed to transfer one word to A. However, if C and B are placed into Sleep mode, the first 24 data bits are directly transferred to A (through C and B); therefore, only 24 clocks are needed.

To wake the device up from transparent mode and return to normal operation, the hardware RESET pin must be toggled.