SLASEE2 February   2018 DAC8771

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      DAC8771 Block Diagram
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Write and Readback Mode
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Current Output Stage
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Buck-Boost Converter
        1. 8.3.3.1 Buck-Boost Converter Outputs
        2. 8.3.3.2 Selecting and Enabling Buck-Boost Converter
        3. 8.3.3.3 Configurable Clamp Feature and Current Output Settling Time
          1. 8.3.3.3.1 Default Mode - CCLP[1:0] = "00"
          2. 8.3.3.3.2 Fixed Clamp Mode - CCLP[1:0] = "01"
          3. 8.3.3.3.3 Auto Learn Mode - CCLP[1:0] = "10"
          4. 8.3.3.3.4 High Side Clamp (HSCLMP)
      4. 8.3.4  Analog Power Supply
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  Internal Reference
      7. 8.3.7  Power-On-Reset
      8. 8.3.8  ALARM Pin
      9. 8.3.9  Power GOOD bit
      10. 8.3.10 Status Register
      11. 8.3.11 Status Mask
      12. 8.3.12 Alarm Action
      13. 8.3.13 Watchdog Timer
      14. 8.3.14 Programmable Slew Rate
      15. 8.3.15 HART Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Peripheral Interface (SPI)
        1. 8.4.1.1 Stand-Alone Operation
        2. 8.4.1.2 Daisy-Chain Operation
      2. 8.4.2 SPI Shift Register
      3. 8.4.3 Write Operation
      4. 8.4.4 Read Operation
      5. 8.4.5 Updating the DAC Outputs and LDAC Pin
        1. 8.4.5.1 Asynchronous Mode
        2. 8.4.5.2 Synchronous Mode
      6. 8.4.6 Hardware RESET Pin
      7. 8.4.7 Hardware CLR Pin
      8. 8.4.8 Frame Error Checking
      9. 8.4.9 DAC Data Calibration
        1. 8.4.9.1 DAC Data Gain and Offset Calibration Registers
    5. 8.5 Register Maps
      1. 8.5.1 Register Maps
        1. 8.5.1.1 DAC8771 Commands
        2. 8.5.1.2 Register Maps and Bit Functions
          1. 8.5.1.2.1  No Operation Register (address = 0x00) [reset = 0x0000]
            1. Table 6. No Operation Field Descriptions
          2. 8.5.1.2.2  Reset Register (address = 0x01) [reset = 0x0000]
            1. Table 7. Reset Register Field Descriptions
          3. 8.5.1.2.3  Reset Config Register (address = 0x02) [reset = 0x0000]
            1. Table 8. Reset Config Register Field Descriptions
          4. 8.5.1.2.4  Select DAC Register (address = 0x03) [reset = 0x0000]
            1. Table 9. Select DAC Register Field Descriptions
          5. 8.5.1.2.5  Configuration DAC Register (address = 0x04) [reset = 0x0000]
            1. Table 10. Configuration DAC Register Field Descriptions
          6. 8.5.1.2.6  DAC Data Register (address = 0x05) [reset = 0x0000]
            1. Table 11. DAC Data Register Field Descriptions
          7. 8.5.1.2.7  Select Buck-Boost Converter Register (address = 0x06) [reset = 0x0000]
            1. Table 12. Select Buck-Boost Converter Register Field Descriptions
          8. 8.5.1.2.8  Configuration Buck-Boost Register (address = 0x07) [reset = 0x0000]
            1. Table 13. Configuration Buck-Boost Register Field Descriptions
          9. 8.5.1.2.9  DAC Channel Calibration Enable Register (address = 0x08) [reset = 0x0000]
            1. Table 14. DAC Channel Calibration Enable Register Field Descriptions
          10. 8.5.1.2.10 DAC Channel Gain Calibration Register (address = 0x09) [reset = 0x0000]
            1. Table 15. DAC Channel Gain Calibration Register Field Descriptions
          11. 8.5.1.2.11 DAC Channel Offset Calibration Register (address = 0x0A) [reset = 0x0000]
            1. Table 16. DAC Channel Offset Calibration Register Field Descriptions
          12. 8.5.1.2.12 Status Register (address = 0x0B) [reset = 0x1000]
            1. Table 17. Status Register Field Descriptions
          13. 8.5.1.2.13 Status Mask Register (address = 0x0C) [reset = 0x0000]
            1. Table 18. Status Mask Register Field Descriptions
          14. 8.5.1.2.14 Alarm Action Register (address = 0x0D) [reset = 0x0000]
            1. Table 19. Alarm Action Register Field Descriptions
          15. 8.5.1.2.15 User Alarm Code Register (address = 0x0E) [reset = 0x0000]
            1. Table 20. User Alarm Code Register Field Descriptions
          16. 8.5.1.2.16 Reserved Register (address = 0x0F) [reset = N/A]
            1. Table 21. Reserved Register Field Descriptions
          17. 8.5.1.2.17 Write Watchdog Timer Register (address = 0x10) [reset = 0x0000]
            1. Table 22. Write Watchdog Timer Register Field Descriptions
          18. 8.5.1.2.18 Reserved Register (address 0x12 - 0xFF) [reset = N/A]
            1. Table 23. Reserved Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Buck-Boost Converter External Component Selection
      2. 9.1.2 Voltage and Current Outputs on a Shared Terminal
      3. 9.1.3 Optimizing Current Output Settling Time with Auto-Learn Mode
      4. 9.1.4 Protection for Industrial Transients
      5. 9.1.5 Implementing HART with DAC8771
    2. 9.2 Typical Application
      1. 9.2.1 Single-Channel, Isolated, EMC and EMI Protected Analog Output Module with Adaptive Power Management
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Typical Characteristics

DAC8771 D001_VOUT_DCDC_DNL_v_code.gifFigure 3. VOUT DNL vs Code (DC/DC Enabled)
DAC8771 D002_VOUT_DNL_v_code.gifFigure 5. VOUT DNL vs Code (DC/DC Disabled)
DAC8771 D003_VOUT_DCDC_TUE_v_code.gifFigure 7. VOUT TUE vs Code (DC/DC Enabled)
DAC8771 D005_VOUT_INL_v_temp.gifFigure 9. VOUT INL vs Temperature
DAC8771 D007_VOUT_TUE_v_temp.gifFigure 11. VOUT TUE vs Temperature
DAC8771 D009_VOUT_FSE_v_temp.gifFigure 13. VOUT Full-Scale Error vs Temperature
DAC8771 D011_VOUT_ZCE_v_temp.gifFigure 15. VOUT Zero-Code Error vs Temperature
DAC8771 D013_VOUT_INL_v_VPOS.gifFigure 17. VOUT INL vs VPOS
DAC8771 D015_VOUT_TUE_v_VPOS.gifFigure 19. VOUT TUE vs VPOS
DAC8771 D017_VOUT_rising_settling.gifFigure 21. VOUT Settling Time, Rising Signal
DAC8771 D020_VOUT_7FFF_8000.gifFigure 23. VOUT Major-Carry Glitch, Positive
DAC8771 D022_VOUT_power_on_glitch.gifFigure 25. VOUT Power-On Glitch
DAC8771 D001_VOUT_DCDC_INL_v_code.gifFigure 4. VOUT INL vs Code (DC/DC Enabled)
DAC8771 D002_VOUT_INL_v_code.gifFigure 6. VOUT INL vs Code (DC/DC Disabled)
DAC8771 D004_VOUT_TUE_v_code.gifFigure 8. VOUT TUE vs Code (DC/DC Disabled)
DAC8771 D006_VOUT_DNL_v_temp.gifFigure 10. VOUT DNL vs Temperature
DAC8771 D008_VOUT_BPZ_v_temp.gifFigure 12. VOUT Bipolar Zero Error vs Temperature
DAC8771 D010_VOUT_GE_v_temp.gifFigure 14. VOUT Gain Error vs Temperature
DAC8771 D012_VOUT_MFSE_v_temp.gifFigure 16. VOUT Negative Full-Scale Error vs Temperature
DAC8771 D014_VOUT_DNL_v_VPOS.gifFigure 18. VOUT DNL vs VPOS
DAC8771 D016_VOUT_SSC.gifFigure 20. VOUT Load Regulation (SCLM = 11)
DAC8771 D018_VOUT_falling_settling.gifFigure 22. VOUT Settling Time, Falling Signal
DAC8771 D021_VOUT_8000_7FFF.gifFigure 24. VOUT Major-Carry Glitch, Negative
DAC8771 D023_VOUT_output_enable_glitch.gifFigure 26. VOUT Output-Enable Glitch
DAC8771 D025_VOUT_DCDC_ripple.gifFigure 28. VOUT DC/DC Ripple (50kHz First-Order Low-Pass Filter)
DAC8771 D027_VOUT_DCDC_PSD.gifFigure 30. VOUT Noise Spectral Density (DC/DC Enabled)
DAC8771 D029_VOUT_IDD_v_temp.gifFigure 32. VOUT Quiescent Current vs Temperature (No Load)
DAC8771 D032_VOUT_clk_feedthrough.gifFigure 34. VOUT Digital Feedthrough
DAC8771 D033_IOUT_DCDC_INL_v_code.gifFigure 36. IOUT INL vs Code (DC/DC Enabled)
DAC8771 D034_IOUT_INL_v_code.gifFigure 38. IOUT INL vs Code (DC/DC Disabled)
DAC8771 D036_IOUT_TUE_v_code.gifFigure 40. IOUT TUE vs Code (DC/DC Enabled)
DAC8771 D038_IOUT_DNL_v_temp.gifFigure 42. IOUT DNL vs Temperature
DAC8771 D040_IOUT_BPZ_v_temp.gifFigure 44. IOUT Bipolar Zero Error vs Temperature
DAC8771 D042_IOUT_GE_v_temp.gifFigure 46. IOUT Gain Error vs Temperature
DAC8771 D044_IOUT_MFSE_v_temp.gifFigure 48. IOUT Negative Full-Scale Error vs Temperature
DAC8771 D045_IOUT_INL_v_VPOS.gifFigure 50. IOUT Unipolar Ranges INL vs VPOS
DAC8771 D046_IOUT_DNL_v_VPOS.gifFigure 52. IOUT Unipolar Ranges DNL vs VPOS
DAC8771 D047_IOUT_TUE_v_VPOS.gifFigure 54. IOUT Unipolar Ranges TUE vs VPOS
DAC8771 D049_IOUT_falling_settling.gifFigure 56. IOUT Settling Time, Falling Signal
DAC8771 D051_IOUT_BP24_falling.gifFigure 58. IOUT Settling Time, Bipolar Range, Falling Signal
DAC8771 D054_IOUT_8000_7FFF.gifFigure 60. IOUT Major Carry Glitch, Negative
DAC8771 D056_IOUT_Output_Enable_glitch.gifFigure 62. IOUT Output Enable Glitch
DAC8771 D058_IOUT_DCDC_ripple.gifFigure 64. IOUT DC/DC Ripple (50kHz First-Order Low-Pass Filter)
DAC8771 D060_IOUT_DCDC_PSD.gifFigure 66. IOUT Noise Spectral Density (DC/DC Enabled)
DAC8771 D062_IOUT_IDD_v_temp.gifFigure 68. IOUT Quiescent Current vs Temperature
DAC8771 D065_IOUT_clk_feedthrough.gifFigure 70. IOUT Digital Feed-Through
DAC8771 D067_VREF_v_load.gifFigure 72. Internal Reference Voltage vs Load
DAC8771 D070_VREF_v_Noise_PSD.gifFigure 74. Internal Reference Voltage Noise Spectral Density (DC/DC Disabled)
DAC8771 D072_VREF_Noise.gifFigure 76. Internal Reference Voltage Noise (DC/DC Disabled)
DAC8771 D075_VPOS_VNEG_enable.gifFigure 78. VPOS & VNEG Enable Settling Time
DAC8771 D078_IOUT_DCDC_Efficiency.gifFigure 80. IOUT DC/DC Efficiency
DAC8771 D080_DCDC_IOUT_Efficiency_v_temp.gifFigure 82. IOUT DC/DC Efficiency vs Temperature
DAC8771 D082_DCDC_IOUT_PDiss_v_temp.gifFigure 84. IOUT Power Dissipation vs Temperature
DAC8771 D085_IOUT_VPOS_Noise_PSD.gifFigure 86. IOUT VPOS Noise Spectral Density
DAC8771 D087_VOUT_VPOS_efficiency_v_load.gifFigure 88. VOUT VPOS Efficiency vs Load
DAC8771 D089_DCDC_VOUT_PDiss_v_load.gifFigure 90. VOUT Power Dissipation vs Load
DAC8771 D091_DCDC_VOUT_Die_temp_v_load.gifFigure 92. VOUT Die Temperature vs Load
DAC8771 D094_VOUT_VNEG_Noise_PSD.gifFigure 94. VPOS VNEG Noise Spectral Density
DAC8771 D024_VOUT_noise.gifFigure 27. VOUT Noise (DC/DC Disabled)
DAC8771 D026_VOUT_PSD.gifFigure 29. VOUT Noise Spectral Density (DC/DC Disabled)
DAC8771 D028_VOUT_IDD_v_code.gifFigure 31. VOUT Quiescent Current vs Code (No Load)
DAC8771 D030_VOUT_IDD_v_vpos.gifFigure 33. VOUT Quiescent Current vs VPOS (No Load)
DAC8771 D033_IOUT_DCDC_DNL_v_code.gifFigure 35. IOUT DNL vs Code (DC/DC Enabled)
DAC8771 D034_IOUT_DNL_v_code.gifFigure 37. IOUT DNL vs Code (DC/DC Disabled)
DAC8771 D035_IOUT_DCDC_TUE_v_code.gifFigure 39. IOUT TUE vs Code (DC/DC Enabled)
DAC8771 D037_IOUT_INL_v_temp.gifFigure 41. IOUT INL vs Temperature
DAC8771 D039_IOUT_TUE_v_temp.gifFigure 43. IOUT TUE vs Temperature
DAC8771 D041_IOUT_FSE_v_temp.gifFigure 45. IOUT Full-Scale Error vs Temperature
DAC8771 D043_IOUT_OE_v_temp.gifFigure 47. IOUT Offset Error vs Temperature
DAC8771 D045_IOUT_BP24_INL_v_VPOS.gifFigure 49. IOUT Bipolar Range INL vs VPOS
DAC8771 D046_IOUT_BP24_DNL_v_VPOS.gifFigure 51. IOUT Bipolar Range DNL vs VPOS
DAC8771 D047_IOUT_BP24_TUE_v_VPOS.gifFigure 53. IOUT Bipolar Range TUE vs VPOS
DAC8771 D048_IOUT_rising_settling.gifFigure 55. IOUT Settling Time, Rising Signal
DAC8771 D050_IOUT_BP24_rising.gifFigure 57. IOUT Settling Time, Bipolar Range, Rising Signal
DAC8771 D053_IOUT_7FFF_8000.gifFigure 59. IOUT Major Carry Glitch, Positive
DAC8771 D055_IOUT_power_on_glitch.gifFigure 61. IOUT Power On Glitch
DAC8771 D057_IOUT_noise.gifFigure 63. IOUT Noise (DC/DC Disabled)
DAC8771 D059_IOUT_PSD.gifFigure 65. IOUT Noise Spectral Density (DC/DC Disabled)
DAC8771 D061_IOUT_IDD_v_code.gifFigure 67. IOUT Quiescent Current vs Code, Bipolar Range
DAC8771 D063_IOUT_IDD_v_VPOS.gifFigure 69. IOUT Quiescent Current vs VPOS
DAC8771 D066_VREF_v_temp.gifFigure 71. Internal Reference Voltage vs Temperature
DAC8771 D068_VREF_v_AVDD.gifFigure 73. Internal Reference Voltage vs AVDD
DAC8771 D071_VREF_DCDC_Noise_PSD.gifFigure 75. Internal Reference Voltage Noise Spectral Density (DC/DC Enabled)
DAC8771 D074_VREF_DCDC_Ripple.gifFigure 77. Internal Reference Voltage DC/DC Ripple
DAC8771 D077_IOUT_VPOS_Efficiency.gifFigure 79. IOUT VPOS Efficiency
DAC8771 D079_DCDC_VPOS_Efficiency_v_temp.gifFigure 81. VPOS Efficiency vs Temperature
DAC8771 D081_DCDC_IOUT_PDiss_v_load.gifFigure 83. IOUT Power Dissipation vs Load
DAC8771 D083_DCDC_IOUT_Die_temp_v_load.gifFigure 85. IOUT Die Temperature vs Load
DAC8771 D086_VOUT_Enable_w_DCDC.gifFigure 87. VOUT Enable VPOS and VNEG Settling Time
DAC8771 D088_VOUT_VPOS_Efficiency_v_temp.gifFigure 89. VOUT VPOS Efficiency vs Temperature
DAC8771 D090_DCDC_VOUT_PDiss_v_temp.gifFigure 91. VOUT Power Dissipation vs Temperature
DAC8771 D093_VOUT_VPOS_Noise_PSD.gifFigure 93. VOUT VPOS Noise Spectral Density
DAC8771 D095_DVDD_IQ_v_Logic_level.gifFigure 95. DVDD Iq vs Logic Level