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  • DACx1401 Single-Channel, 16-Bit and 12-Bit, High-Voltage Output DACs With Precision Internal Reference

    • SLASEH4A November   2023  – December 2024 DAC61401 , DAC81401

      PRODUCTION DATA  

  • CONTENTS
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  • DACx1401 Single-Channel, 16-Bit and 12-Bit, High-Voltage Output DACs With Precision Internal Reference
  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements - Write, IOVDD = 1.7V to 2.7V
    7. 5.7  Timing Requirements - Write, IOVDD = 2.7V to 5.5V
    8. 5.8  Timing Requirements - Read and Daisy Chain, FSDO = 0, IOVDD = 1.7V to 2.7V
    9. 5.9  Timing Requirements - Read and Daisy Chain, FSDO = 1, IOVDD = 1.7V to 2.7V
    10. 5.10 Timing Requirements - Read and Daisy Chain, FSDO = 0, IOVDD = 2.7V to 5.5V
    11. 5.11 Timing Requirements - Read and Daisy Chain, FSDO = 1, IOVDD = 2.7V to 5.5V
    12. 5.12 Timing Diagrams
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 R-2R Ladder DAC
      3. 6.3.3 Programmable Gain Output Buffer
      4. 6.3.4 Sense Pins
      5. 6.3.5 DAC Register Structure
        1. 6.3.5.1 Output Update
        2. 6.3.5.2 Software Clear
          1. 6.3.5.2.1 Software Reset Mode
      6. 6.3.6 Internal Reference
      7. 6.3.7 Power-Supply Sequence
        1. 6.3.7.1 Power-On Reset (POR)
      8. 6.3.8 Thermal Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Down Mode
    5. 6.5 Programming
      1. 6.5.1 Stand-Alone Operation
      2. 6.5.2 Daisy-Chain Operation
      3. 6.5.3 Frame Error Checking
  8. 7 Register Map
    1. 7.1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Key Components
        2. 8.2.2.2 Compensation Capacitor
        3. 8.2.2.3 Gain Stage
        4. 8.2.2.4 Attenuation and Buffer Stage
        5. 8.2.2.5 External Power Supply
        6. 8.2.2.6 Protection Design
        7. 8.2.2.7 Design Accuracy
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE
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Data Sheet

DACx1401 Single-Channel, 16-Bit and 12-Bit, High-Voltage Output DACs With Precision Internal Reference

1 Features

  • Exceptional performance: 1LSB INL/DNL (maximum)
  • Ultra-low glitch energy: 1nV-s
  • Wide power supply:
    • Unipolar mode: +4.5V to +41.5V
    • Bipolar mode: ±4.5V to ±21.5V
  • 14 user-programmable output ranges
    • ±5V, ±10V, ±20V
    • 0V to 5V, 0V to 10V, 0V to 20V, 0V to 40V
    • 20% overrange (except ±20V and 0V to 40V)
  • Integrated 10ppm/°C, 2.5V precision reference
  • Reliability features:
    • Cyclic redundancy check (CRC)
    • Fault pin
  • 50MHz, 4-wire SPI-compatible interface
    • Readback
    • Daisy-chain
  • Temperature range: –55°C to +125°C
  • Packages:
    • 20-pin TSSOP (PW)
    • 16-pin WQFN (RTE)

2 Applications

  • Semiconductor test and ATE
  • Lab and field instrumentation
  • PLC, DCS, and PAC
  • Analog output module
  • Servo drive control module

3 Description

The 16-bit DAC81401 and 12-bit DAC61401 (DACx1401) devices are a pin-compatible family of single-channel, buffered, high-voltage-output digital-to-analog converters (DACs) with an integrated 2.5V internal reference. These devices are specified monotonic and provide an exceptional linearity of less than 1LSB (maximum).

The DACx1401 offer bipolar output voltages of ±20V, ±10V, ±5V, and full-scale unipolar output voltages of 40V, 10V, and 5V. The DAC output range is programmable.

The DACx1401 incorporate a power-on-reset (POR) circuit that powers up the DAC output and keeps the devices in power-down mode until the outputs enable.

Communication to the devices is done through a high-speed, 4-wire serial interface compatible with industry-standard microprocessors and microcontrollers supporting 1.7V to 5.5V operation.

The DACx1401 are characterized for operation over the temperature range of –55°C to +125°C, and are available in a small 16-pin QFN and 20-pin TSSOP package.

Device Information
PART NUMBER RESOLUTION PACKAGE(1)
DAC61401 12-bit PW (TSSOP, 20)
RTE (WQFN, 16)
DAC81401 16-bit PW (TSSOP, 20)
RTE (WQFN, 16)
(1) For more information, see Section 11.
DAC61401 DAC81401 DACx1401 Block Diagram DACx1401 Block Diagram

4 Pin Configuration and Functions

Figure 4-1 PW Package, 20-Pin TSSOP (Top View)
Figure 4-2 RTE Package, 16-Pin WQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
PW (TSSOP) RTE (WQFN)
AVDD 5 6 Power Power supply
AVSS 3 5 Power Negative power supply
CCOMP 7 7 Input External compensation capacitor connection pin for VOUT.
Addition of the external capacitor (470pF, typical) improves the stability with high capacitive loads (up to 1μF) at the VOUT pin by reducing the bandwidth of the output amplifier at the expense of increased settling time.
FAULT 12 11 Output FAULT pin. Open drain output. External 10kΩ pullup resistor required. The pin goes low (active) when the FAULT condition is detected.
GND 19 1 Ground Digital and analog ground, connects to 0V
IOVDD 17 16 Input IO pin power supply
NC 4, 6, 8, 18 — — Must be left unconnected, pin floating
SCLK 14 13 Input Serial clock input of serial peripheral interface (SPI). Data can be transferred at rates up to 50MHz. Schmitt-trigger logic input
SDIN 15 14 Input Serial data input. Data are clocked into the register on the falling edge of the serial clock input. Schmitt-trigger logic input
SDO 13 12 Output Serial data output. Data are valid on the rising or falling edge of SCLK set by FSDO.
SYNC 16 15 Input SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless SYNC is low. When SYNC is high, SDO is in Hi-Z.
VDD 20 2 Power Digital and analog power supply
VOUT 9 8 Output DAC voltage output pin
VREFGND 2 4 Input Reference ground, connects to 0V
VREFIO 1 3 Input/output Internal reference output or external reference input. Connect a 150nF capacitor to ground.
VSENSEN 11 10 Input Connect to 0V
VSENSEP 10 9 Input Sense output pin for the positive voltage output load connection

 
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