SLASEK6 October   2017 MSP432E411Y

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-3 Signal Descriptions
    4. 4.4 GPIO Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended DC Operating Conditions
    5. 5.5  Recommended GPIO Operating Characteristics
    6. 5.6  Recommended Fast GPIO Pad Operating Conditions
    7. 5.7  Recommended Slow GPIO Pad Operating Conditions
    8. 5.8  GPIO Current Restrictions
    9. 5.9  I/O Reliability
    10. 5.10 Current Consumption
    11. 5.11 Peripheral Current Consumption
    12. 5.12 LDO Regulator Characteristics
    13. 5.13 Power Dissipation
    14. 5.14 Thermal Resistance Characteristics, 212-Pin ZAD (NFBGA) Package
    15. 5.15 Timing and Switching Characteristics
      1. 5.15.1  Load Conditions
      2. 5.15.2  Power Supply Sequencing
        1. 5.15.2.1 Power and Brownout
          1. Table 5-3 Power and Brownout Levels
          2. 5.15.2.1.1 VDDA Levels
          3. 5.15.2.1.2 VDD Levels
          4. 5.15.2.1.3 VDDC Levels
          5. 5.15.2.1.4 VDD Glitch Response
          6. 5.15.2.1.5 VDD Droop Response
      3. 5.15.3  Reset Timing
        1. Table 5-4 Reset Characteristics
      4. 5.15.4  Clock Specifications
        1. 5.15.4.1 PLL Specifications
          1. Table 5-5 Phase Locked Loop (PLL) Characteristics
          2. 5.15.4.1.1 PLL Configuration
        2. 5.15.4.2 PIOSC Specifications
        3. 5.15.4.3 Low-Frequency Oscillator Specifications
          1. Table 5-9 Low-Frequency Oscillator Characteristics
        4. 5.15.4.4 Hibernation Low-Frequency Oscillator Specifications
          1. Table 5-10 Hibernation External Oscillator (XOSC) Input Characteristics
          2. Table 5-11 Hibernation Internal Low-Frequency Oscillator Clock Characteristics
        5. 5.15.4.5 Main Oscillator Specifications
          1. Table 5-12 Main Oscillator Input Characteristics
        6. 5.15.4.6 Main Oscillator Specification WIth ADC
          1. Table 5-14 System Clock Characteristics With ADC Operation
        7. 5.15.4.7 System Clock Characteristics With USB Operation
          1. Table 5-15 System Clock Characteristics With USB Operation
      5. 5.15.5  Sleep Modes
        1. Table 5-16 Wake From Sleep Characteristics
        2. Table 5-17 Wake From Deep Sleep Characteristics
      6. 5.15.6  Hibernation Module
        1. Table 5-18 Hibernation Module Battery Characteristics
        2. Table 5-19 Hibernation Module Characteristics
        3. Table 5-20 Hibernation Module Tamper I/O Characteristics
      7. 5.15.7  Flash Memory
        1. Table 5-21 Flash Memory Characteristics
      8. 5.15.8  EEPROM
        1. Table 5-22 EEPROM Characteristics
      9. 5.15.9  Input/Output Pin Characteristics
        1. Table 5-23 Fast GPIO Module Characteristics
        2. Table 5-24 Slow GPIO Module Characteristics
        3. 5.15.9.1    Types of I/O Pins and ESD Protection
          1. 5.15.9.1.1 Hibernate WAKE pin
            1. Table 5-25 Pad Voltage and Current Characteristics for Hibernate WAKE Pin
          2. 5.15.9.1.2 Nonpower I/O Pins
            1. Table 5-26 Nonpower I/O Pad Voltage and Current Characteristics
      10. 5.15.10 External Peripheral Interface (EPI)
        1. Table 5-28 EPI SDRAM Characteristics
        2. Table 5-29 EPI SDRAM Interface Characteristics
        3. Table 5-30 EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics
        4. Table 5-31 EPI General-Purpose Interface Characteristics
        5. Table 5-32 EPI PSRAM Interface Characteristics
      11. 5.15.11 Analog-to-Digital Converter (ADC)
        1. Table 5-33 Electrical Characteristics for ADC at 1 Msps
        2. Table 5-34 Electrical Characteristics for ADC at 2 Msps
      12. 5.15.12 Synchronous Serial Interface (SSI)
        1. Table 5-35 SSI Characteristics
        2. Table 5-36 Bi- and Quad-SSI Characteristics
      13. 5.15.13 Inter-Integrated Circuit (I2C) Interface
        1. Table 5-37 I2C Characteristics
      14. 5.15.14 Ethernet Controller
        1. 5.15.14.1 DC Characteristics
          1. Table 5-38 Ethernet PHY DC Characteristics
        2. 5.15.14.2 Clock Characteristics for Ethernet
          1. Table 5-39 MOSC 25-MHz Crystal Specification
          2. Table 5-40 MOSC Single-Ended 25-MHz Oscillator Specification
          3. Table 5-41 EN0RREF_CLK 50-MHz Oscillator Specification
        3. 5.15.14.3 AC Characteristics
          1. Table 5-42 Ethernet Controller Enable and Software Reset Timing
          2. Table 5-43 MII Serial Management Timing
          3. Table 5-44 100-Mbps MII Transmit Timing
          4. Table 5-45 100-Mbps MII Receive Timing
          5. Table 5-46 100Base-TX Transmit Timing
          6. Table 5-47 10-Mbps MII Transmit Timing
          7. Table 5-48 10-Mbps MII Receive Timing
          8. Table 5-49 10Base-T Normal Link Pulse Timing
          9. Table 5-50 Auto-Negotiation Fast Link Pulse (FLP) Timing
          10. Table 5-51 100Base-TX Signal Detect Timing
          11. Table 5-52 RMII Transmit Timing
          12. Table 5-53 RMII Receive Timing
      15. 5.15.15 Universal Serial Bus (USB) Controller
        1. Table 5-54 ULPI Interface Timing
      16. 5.15.16 LCD Controller
        1. Table 5-55 LCD Controller Load Capacitance Limits
        2. 5.15.16.1   LCD Interface Display Driver (LIDD Mode)
          1. Table 5-56 LCD Switching Characteristics
          2. Table 5-57 Timing Requirements for LCDDATA in LIDD Mode
          3. 5.15.16.1.1 Hitachi Mode
          4. 5.15.16.1.2 Motorola 6800 Mode
          5. 5.15.16.1.3 Intel 8080 Mode
        3. 5.15.16.2   LCD Raster Mode
          1. Table 5-58 Switching Characteristics for LCD Raster Mode
      17. 5.15.17 Analog Comparator
        1. Table 5-59 Analog Comparator Characteristics
        2. Table 5-60 Analog Comparator Characteristics
        3. Table 5-61 Analog Comparator Voltage Reference Characteristics
        4. Table 5-62 Analog Comparator Voltage Reference Characteristics
      18. 5.15.18 Pulse-Width Modulator (PWM)
        1. Table 5-63 PWM Timing Characteristics
      19. 5.15.19 Emulation and Debug
        1. Table 5-64 JTAG Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Arm Cortex-M4F Processor Core
      1. 6.3.1 Processor Core
      2. 6.3.2 System Timer (SysTick)
      3. 6.3.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.3.4 System Control Block (SCB)
      5. 6.3.5 Memory Protection Unit (MPU)
      6. 6.3.6 Floating-Point Unit (FPU)
    4. 6.4 On-Chip Memory
      1. 6.4.1 SRAM
      2. 6.4.2 Flash Memory
      3. 6.4.3 ROM
      4. 6.4.4 EEPROM
      5. 6.4.5 Memory Map
    5. 6.5 Peripherals
      1. 6.5.1  External Peripheral Interface (EPI)
      2. 6.5.2  Cyclical Redundancy Check (CRC)
      3. 6.5.3  Advanced Encryption Standard (AES) Accelerator
      4. 6.5.4  Data Encryption Standard (DES) Accelerator
      5. 6.5.5  Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5) Accelerator
      6. 6.5.6  Serial Communications Peripherals
        1. 6.5.6.1 Ethernet MAC and PHY
        2. 6.5.6.2 Controller Area Network (CAN)
        3. 6.5.6.3 Universal Serial Bus (USB)
        4. 6.5.6.4 Universal Asynchronous Receiver/Transmitter (UART)
        5. 6.5.6.5 1-Wire Master Module
        6. 6.5.6.6 Inter-Integrated Circuit (I2C)
        7. 6.5.6.7 Quad Synchronous Serial Interface (QSSI)
      7. 6.5.7  System Integration
        1. 6.5.7.1 Direct Memory Access (DMA)
        2. 6.5.7.2 System Control and Clocks
        3. 6.5.7.3 Programmable Timers
        4. 6.5.7.4 Capture Compare PWM (CCP) Pins
        5. 6.5.7.5 Hibernation (HIB) Module
        6. 6.5.7.6 Watchdog Timers
        7. 6.5.7.7 Programmable GPIOs
      8. 6.5.8  LCD Controller
      9. 6.5.9  Advanced Motion Control
        1. 6.5.9.1 Pulse Width Modulation (PWM)
        2. 6.5.9.2 Quadrature Encoder With Index (QEI) Module
      10. 6.5.10 Analog
        1. 6.5.10.1 ADC
        2. 6.5.10.2 Analog Comparators
      11. 6.5.11 JTAG and Arm Serial Wire Debug
      12. 6.5.12 Peripheral Memory Map
    6. 6.6 Identification
    7. 6.7 Boot Modes
  7. 7Applications, Implementation, and Layout
    1. 7.1 System Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Community Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Table 5-12 Main Oscillator Input Characteristics

over operating free-air temperature (unless otherwise noted)(2)
PARAMETER MINNOMMAXUNIT
fMOSC Parallel resonance frequency 4 (1) 25 MHz
fREF_XTAL_BYPASS External clock reference (PLL in BYPASS mode) 0 120 MHz
C1, C2 External load capacitance on OSC0, OSC1 pins (3) 12 24 pF
CPKG Device package stray shunt capacitance (3) 0.5 pF
CPCB PCB stray shunt capacitance (3) 0.5 pF
CSHUNT Total shunt capacitance (3) 4 pF
ESR Crystal effective series resistance 4 MHz (4)(5) 300 Ω
6 MHz (4)(5) 200
8 MHz (4)(5) 130
12 MHz (4)(5) 120
16 MHz (4)(5) 100
25 MHz (4)(5) 50
DL Oscillator output drive level(7) OSCPWR mW
TSTART Oscillator start-up time, when using a crystal (6) 18 ms
VIH CMOS input high level, when using an external oscillator 0.65 × VDD VDD V
VIL CMOS input low level, when using an external oscillator GND 0.35 × VDD V
VHYS CMOS input buffer hysteresis, when using an external oscillator 150 mV
DCOSC_EXT External clock reference duty cycle 45% 55%
(1) 5 MHz is the minimum when using the PLL.
(2) See Table 5-39 and Table 5-40 for additional Ethernet crystal requirements.
(3) See the additional information about the load capacitors following this table.
(4) Crystal ESR specified by crystal manufacturer.
(5) Crystal vendors can be contacted to confirm these specifications are met for a specific crystal part number if the vendors generic crystal datasheet show limits outside of these specifications.
(6) Oscillator start-up time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation such that the internal clock is valid.
(7) OSCPWR = (2 × π × FP × CL × 2.5)2 × ESR / 2. An estimation of the typical power delivered to the crystal is based on the CL, FP and ESR parameters of the crystal in the circuit as calculated by the OSCPWR equation. Ensure that the value calculated for OSCPWR does not exceed the crystal's drive-level maximum.

The load capacitors added on the board, C1 and C2, should be chosen such that Equation 4 is satisfied (see Table 5-12 for typical values and Table 5-13 for detailed crystal parameter information).

Equation 4. CL = (C1 × C2) / (C1 + C2) + CSHUNT

where

  • CL = load capacitance specified by crystal manufacturer
  • CSHUNT = C0 + CPKG + CPCB (total shunt capacitance seen across OSC0 and OSC1 crystal inputs)
  • CPKG, CPCB = Mutual capacitance as measured across the OSC0 and OSC1 pins excluding the crystal
  • C0 = Shunt capacitance of crystal specified by the crystal manufacturer

Table 5-13 lists part numbers of crystals that have been simulated and confirmed to operate within the specifications in Table 5-12. Other crystals that have nearly identical crystal parameters can be expected to work as well.

In Table 5-13, the crystal parameters labeled C0, C1, and L1 are values that are obtained from the crystal manufacturer. These numbers are usually a result of testing a relevant batch of crystals on a network analyzer. The parameters labeled ESR, DL, and CL are maximum numbers usually available in the data sheet for a crystal.

Table 5-13 also includes three columns of Recommended Component Values. These values apply to system board components. C1 and C2 are the values in picofarads of the load capacitors that should be put on each leg of the crystal pins to ensure oscillation at the correct frequency. Rs is the value in kΩ of a resistor that is placed in series with the crystal between the OSC1 pin and the crystal pin. Rs dissipates some of the power so the Max Dl crystal parameter is not exceeded. Only use the recommended C1, C2, and Rs values with the associated crystal part. The values in the table were used in the simulation to ensure crystal start-up and to determine the worst-case drive level (WC DL). The value in the WC DL column should not be greater than the Max DL crystal parameter. The WC DL value can be used to determine if a crystal with similar parameter values but a lower Max DL value is acceptable.

Table 5-13 Crystal Parameters

Manufacturer Manufacturer Part NumberHolder Package Size (mm × mm)Frequency (MHz) Crystal Specification (Tolerance / Stability) Crystal ParametersRecommended Component ValuesWC DL (µW)
Typical Values Max Values
C0 (pF)C1 (fF)L1 (mH)ESR (Ω) Max DL (µW)CL (pf) C1 (pF)C2 (pF)Rs (kΩ)
NDK NX8045GB-4.000M-STD-CJL-5 NX8045GB 8 × 4.5 4 30 / 50 ppm 1.00 2.70 598.10 300 500 8 12 12 0 132
FOX FQ1045A-4 2-SMD 10 × 4.5 4 30 / 30 ppm 1.18 4.05 396.00 150 500 10 14 14 0 103
NDK NX8045GB-5.000M-STD-CSF-4 NX8045GB 8 × 4.5 5 30 / 50 ppm 1.00 2.80 356.50 250 500 8 12 12 0 164
NDK NX8045GB-6.000M-STD-CSF-4 NX8045GB 8 × 4.5 6 30 / 50 ppm 1.30 4.10 173.20 250 500 8 12 12 0 214
FOX FQ1045A-6 2-SMD 10 × 4.5 6 30 / 30 ppm 1.37 6.26 112.30 150 500 10 14 14 0 209
NDK NX8045GB-8.000M-STD-CSF-6 NX8045GB 8 × 4.5 8 30 / 50 ppm 1.00 2.80 139.30 200 500 8 12 12 0 277
FOX FQ7050B-8 4-SMD 7 × 5 8 30 / 30 ppm 1.95 6.69 59.10 80 500 10 14 14 0 217
ECS ECS-80-16-28A-TR HC49/US 12.5 × 4.85 8 50 / 30 ppm 1.82 4.90 85.70 80 500 16 24 24 0 298
Abracon AABMM-12.0000MHz-10-D-1-X-T ABMM 7.2 × 5.2 12 10 / 20 ppm 2.37 8.85 20.5 50 500 10 12 12 2.0 (1) 124
NDK NX3225GA-12.000MHZ-STD-CRG-2 NX3225GA 3.2 × 2.5 12 20 / 30 ppm 0.70 2.20 81.00 100 200 8 12 12 2.5 147
NDK NX5032GA-12.000MHZ-LN-CD-1 NX5032GA 5 × 3.2 12 30 / 50 ppm 0.93 3.12 56.40 120 500 8 12 12 0 362
FOX FQ5032B-12 4-SMD 5 × 3.2 12 30 / 30 ppm 1.16 4.16 42.30 80 500 10 14 14 0 370
Abracon AABMM-16.0000MHz-10-D-1-X-T ABMM 7.2 × 5.2 16 10 / 20 ppm 3.00 11.00 9.30 50 500 10 12 12 2.0 (1) 143
Ecliptek ECX-6595-16.000M HC-49/UP 13.3 × 4.85 16 15 / 30 ppm 3.00 12.7 8.1 50 1000 10 12 12 2.0 (1) 139
NDK NX3225GA-16.000MHZ-STD-CRG-2 NX3225GA 3.2 × 2.5 16 20 / 30 ppm 1.00 2.90 33.90 80 200 8 12 12 2 188
NDK NX5032GA-16.000MHZ-LN-CD-1 NX5032GA 5 × 3.2 16 30 / 50 ppm 1.02 3.82 25.90 120 (2) 500 8 10 10 0 437
ECS ECS-160-9-42-CKM-TR ECX-42 4 × 2.5 16 10 / 10 ppm 1.47 3.90 25.84 60 300 9 12 12 0.5 289
Abracon AABMM-25.0000MHz-10-D-1-X-T ABMM 7.2 × 5.2 25 10 / 20 ppm 3.00 11.00 3.70 50 500 10 12 12 2.0 (1) 158
Ecliptek ECX-6593-25.000M HC-49/UP 13.3 × 4.85 25 15 / 30 ppm 3.00 12.8 3.2 40 1000 10 12 12 1.5 (1) 159
NDK NX3225GA-25.000MHZ-STD-CRG-2 NX3225GA 3.2 × 2.5 25 20 / 30 ppm 1.10 4.70 8.70 50 200 8 12 12 2 181
NDK NX5032GA-25.000MHZ-LD-CD-1 NX5032GA 5 × 3.2 25 30 / 50 ppm 1.3 5.1 7.1 70 500 8 10 10 1.0 (1) 216
12 12 0.75 (3) 269
AURIS Q-25.000M-HC3225/4-F-30-30-E-12-TR HC3225/4 3.2 × 2.5 25 30 / 30 ppm 1.58 5.01 8.34 50 500 12 16 16 1 331
FOX FQ5032B-25 4-SMD 5 × 3.2 25 30 / 30 ppm 1.69 7.92 5.13 50 500 10 14 14 0.5 433
TXC 7A2570018 NX5032GA 5 × 3.2 25 20 / 25 ppm 2.0 6.7 6.1 30 350 10 12 12 2.0 (3) 124
(1) RS values as low as 0 Ω can be used. Using a lower RS value causes the WC DL to increase toward the maximum DL of the crystal.
(2) Although this ESR value is outside of the recommended crystal ESR maximum for this frequency, this crystal has been simulated to confirm proper operation and is valid for use with this device.
(3) RS values as low as 500 Ω can be used. Using a lower RS value causes the WC DL to increase toward the maximum DL of the crystal.