SLASEK6 October   2017 MSP432E411Y

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-3 Signal Descriptions
    4. 4.4 GPIO Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended DC Operating Conditions
    5. 5.5  Recommended GPIO Operating Characteristics
    6. 5.6  Recommended Fast GPIO Pad Operating Conditions
    7. 5.7  Recommended Slow GPIO Pad Operating Conditions
    8. 5.8  GPIO Current Restrictions
    9. 5.9  I/O Reliability
    10. 5.10 Current Consumption
    11. 5.11 Peripheral Current Consumption
    12. 5.12 LDO Regulator Characteristics
    13. 5.13 Power Dissipation
    14. 5.14 Thermal Resistance Characteristics, 212-Pin ZAD (NFBGA) Package
    15. 5.15 Timing and Switching Characteristics
      1. 5.15.1  Load Conditions
      2. 5.15.2  Power Supply Sequencing
        1. 5.15.2.1 Power and Brownout
          1. Table 5-3 Power and Brownout Levels
          2. 5.15.2.1.1 VDDA Levels
          3. 5.15.2.1.2 VDD Levels
          4. 5.15.2.1.3 VDDC Levels
          5. 5.15.2.1.4 VDD Glitch Response
          6. 5.15.2.1.5 VDD Droop Response
      3. 5.15.3  Reset Timing
        1. Table 5-4 Reset Characteristics
      4. 5.15.4  Clock Specifications
        1. 5.15.4.1 PLL Specifications
          1. Table 5-5 Phase Locked Loop (PLL) Characteristics
          2. 5.15.4.1.1 PLL Configuration
        2. 5.15.4.2 PIOSC Specifications
        3. 5.15.4.3 Low-Frequency Oscillator Specifications
          1. Table 5-9 Low-Frequency Oscillator Characteristics
        4. 5.15.4.4 Hibernation Low-Frequency Oscillator Specifications
          1. Table 5-10 Hibernation External Oscillator (XOSC) Input Characteristics
          2. Table 5-11 Hibernation Internal Low-Frequency Oscillator Clock Characteristics
        5. 5.15.4.5 Main Oscillator Specifications
          1. Table 5-12 Main Oscillator Input Characteristics
        6. 5.15.4.6 Main Oscillator Specification WIth ADC
          1. Table 5-14 System Clock Characteristics With ADC Operation
        7. 5.15.4.7 System Clock Characteristics With USB Operation
          1. Table 5-15 System Clock Characteristics With USB Operation
      5. 5.15.5  Sleep Modes
        1. Table 5-16 Wake From Sleep Characteristics
        2. Table 5-17 Wake From Deep Sleep Characteristics
      6. 5.15.6  Hibernation Module
        1. Table 5-18 Hibernation Module Battery Characteristics
        2. Table 5-19 Hibernation Module Characteristics
        3. Table 5-20 Hibernation Module Tamper I/O Characteristics
      7. 5.15.7  Flash Memory
        1. Table 5-21 Flash Memory Characteristics
      8. 5.15.8  EEPROM
        1. Table 5-22 EEPROM Characteristics
      9. 5.15.9  Input/Output Pin Characteristics
        1. Table 5-23 Fast GPIO Module Characteristics
        2. Table 5-24 Slow GPIO Module Characteristics
        3. 5.15.9.1    Types of I/O Pins and ESD Protection
          1. 5.15.9.1.1 Hibernate WAKE pin
            1. Table 5-25 Pad Voltage and Current Characteristics for Hibernate WAKE Pin
          2. 5.15.9.1.2 Nonpower I/O Pins
            1. Table 5-26 Nonpower I/O Pad Voltage and Current Characteristics
      10. 5.15.10 External Peripheral Interface (EPI)
        1. Table 5-28 EPI SDRAM Characteristics
        2. Table 5-29 EPI SDRAM Interface Characteristics
        3. Table 5-30 EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics
        4. Table 5-31 EPI General-Purpose Interface Characteristics
        5. Table 5-32 EPI PSRAM Interface Characteristics
      11. 5.15.11 Analog-to-Digital Converter (ADC)
        1. Table 5-33 Electrical Characteristics for ADC at 1 Msps
        2. Table 5-34 Electrical Characteristics for ADC at 2 Msps
      12. 5.15.12 Synchronous Serial Interface (SSI)
        1. Table 5-35 SSI Characteristics
        2. Table 5-36 Bi- and Quad-SSI Characteristics
      13. 5.15.13 Inter-Integrated Circuit (I2C) Interface
        1. Table 5-37 I2C Characteristics
      14. 5.15.14 Ethernet Controller
        1. 5.15.14.1 DC Characteristics
          1. Table 5-38 Ethernet PHY DC Characteristics
        2. 5.15.14.2 Clock Characteristics for Ethernet
          1. Table 5-39 MOSC 25-MHz Crystal Specification
          2. Table 5-40 MOSC Single-Ended 25-MHz Oscillator Specification
          3. Table 5-41 EN0RREF_CLK 50-MHz Oscillator Specification
        3. 5.15.14.3 AC Characteristics
          1. Table 5-42 Ethernet Controller Enable and Software Reset Timing
          2. Table 5-43 MII Serial Management Timing
          3. Table 5-44 100-Mbps MII Transmit Timing
          4. Table 5-45 100-Mbps MII Receive Timing
          5. Table 5-46 100Base-TX Transmit Timing
          6. Table 5-47 10-Mbps MII Transmit Timing
          7. Table 5-48 10-Mbps MII Receive Timing
          8. Table 5-49 10Base-T Normal Link Pulse Timing
          9. Table 5-50 Auto-Negotiation Fast Link Pulse (FLP) Timing
          10. Table 5-51 100Base-TX Signal Detect Timing
          11. Table 5-52 RMII Transmit Timing
          12. Table 5-53 RMII Receive Timing
      15. 5.15.15 Universal Serial Bus (USB) Controller
        1. Table 5-54 ULPI Interface Timing
      16. 5.15.16 LCD Controller
        1. Table 5-55 LCD Controller Load Capacitance Limits
        2. 5.15.16.1   LCD Interface Display Driver (LIDD Mode)
          1. Table 5-56 LCD Switching Characteristics
          2. Table 5-57 Timing Requirements for LCDDATA in LIDD Mode
          3. 5.15.16.1.1 Hitachi Mode
          4. 5.15.16.1.2 Motorola 6800 Mode
          5. 5.15.16.1.3 Intel 8080 Mode
        3. 5.15.16.2   LCD Raster Mode
          1. Table 5-58 Switching Characteristics for LCD Raster Mode
      17. 5.15.17 Analog Comparator
        1. Table 5-59 Analog Comparator Characteristics
        2. Table 5-60 Analog Comparator Characteristics
        3. Table 5-61 Analog Comparator Voltage Reference Characteristics
        4. Table 5-62 Analog Comparator Voltage Reference Characteristics
      18. 5.15.18 Pulse-Width Modulator (PWM)
        1. Table 5-63 PWM Timing Characteristics
      19. 5.15.19 Emulation and Debug
        1. Table 5-64 JTAG Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Arm Cortex-M4F Processor Core
      1. 6.3.1 Processor Core
      2. 6.3.2 System Timer (SysTick)
      3. 6.3.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.3.4 System Control Block (SCB)
      5. 6.3.5 Memory Protection Unit (MPU)
      6. 6.3.6 Floating-Point Unit (FPU)
    4. 6.4 On-Chip Memory
      1. 6.4.1 SRAM
      2. 6.4.2 Flash Memory
      3. 6.4.3 ROM
      4. 6.4.4 EEPROM
      5. 6.4.5 Memory Map
    5. 6.5 Peripherals
      1. 6.5.1  External Peripheral Interface (EPI)
      2. 6.5.2  Cyclical Redundancy Check (CRC)
      3. 6.5.3  Advanced Encryption Standard (AES) Accelerator
      4. 6.5.4  Data Encryption Standard (DES) Accelerator
      5. 6.5.5  Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5) Accelerator
      6. 6.5.6  Serial Communications Peripherals
        1. 6.5.6.1 Ethernet MAC and PHY
        2. 6.5.6.2 Controller Area Network (CAN)
        3. 6.5.6.3 Universal Serial Bus (USB)
        4. 6.5.6.4 Universal Asynchronous Receiver/Transmitter (UART)
        5. 6.5.6.5 1-Wire Master Module
        6. 6.5.6.6 Inter-Integrated Circuit (I2C)
        7. 6.5.6.7 Quad Synchronous Serial Interface (QSSI)
      7. 6.5.7  System Integration
        1. 6.5.7.1 Direct Memory Access (DMA)
        2. 6.5.7.2 System Control and Clocks
        3. 6.5.7.3 Programmable Timers
        4. 6.5.7.4 Capture Compare PWM (CCP) Pins
        5. 6.5.7.5 Hibernation (HIB) Module
        6. 6.5.7.6 Watchdog Timers
        7. 6.5.7.7 Programmable GPIOs
      8. 6.5.8  LCD Controller
      9. 6.5.9  Advanced Motion Control
        1. 6.5.9.1 Pulse Width Modulation (PWM)
        2. 6.5.9.2 Quadrature Encoder With Index (QEI) Module
      10. 6.5.10 Analog
        1. 6.5.10.1 ADC
        2. 6.5.10.2 Analog Comparators
      11. 6.5.11 JTAG and Arm Serial Wire Debug
      12. 6.5.12 Peripheral Memory Map
    6. 6.6 Identification
    7. 6.7 Boot Modes
  7. 7Applications, Implementation, and Layout
    1. 7.1 System Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Community Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

6.5.12 Peripheral Memory Map

Table 6-3 lists the address for each peripheral.

NOTE

Within the memory map, attempts to read or write addresses in reserved spaces result in a bus fault. In addition, attempts to write addresses in the flash range also result in a bus fault.

Table 6-3 Memory Map

STARTENDDESCRIPTIONREGISTERS
0x4000.0000 0x4000.0FFF Watchdog Timer 0 Table 6-34
0x4000.1000 0x4000.1FFF Watchdog Timer 1 Table 6-34
0x4000.2000 0x4000.3FFF Reserved
0x4000.4000 0x4000.4FFF GPIO Port A Table 6-18
0x4000.5000 0x4000.5FFF GPIO Port B Table 6-18
0x4000.6000 0x4000.6FFF GPIO Port C Table 6-18
0x4000.7000 0x4000.7FFF GPIO Port D Table 6-18
0x4000.8000 0x4000.8FFF SSI0 Table 6-27
0x4000.9000 0x4000.9FFF SSI1 Table 6-27
0x4000.A000 0x4000.AFFF SSI2 Table 6-27
0x4000.B000 0x4000.BFFF SSI3 Table 6-27
0x4000.C000 0x4000.CFFF UART0 Table 6-32
0x4000.D000 0x4000.DFFF UART1 Table 6-32
0x4000.E000 0x4000.EFFF UART2 Table 6-32
0x4000.F000 0x4000.FFFF UART3 Table 6-32
0x4001.0000 0x4001.0FFF UART4 Table 6-32
0x4001.1000 0x4001.1FFF UART5 Table 6-32
0x4001.2000 0x4001.2FFF UART6 Table 6-32
0x4001.3000 0x4001.3FFF UART7 Table 6-32
0x4001.4000 0x4001.FFFF Reserved
0x4002.0000 0x4002.0FFF I2C 0 Table 6-21
0x4002.1000 0x4002.1FFF I2C 1 Table 6-21
0x4002.2000 0x4002.2FFF I2C 2 Table 6-21
0x4002.3000 0x4002.3FFF I2C 3 Table 6-21
0x4002.4000 0x4002.4FFF GPIO Port E Table 6-18
0x4002.5000 0x4002.5FFF GPIO Port F Table 6-18
0x4002.6000 0x4002.6FFF GPIO Port G Table 6-18
0x4002.7000 0x4002.7FFF GPIO Port H Table 6-18
0x4002.8000 0x4002.8FFF PWM 0 Table 6-25
0x4002.9000 0x4002.BFFF Reserved
0x4002.C000 0x4002.CFFF QEI0 Table 6-26
0x4002.D000 0x4002.FFFF Reserved
0x4003.0000 0x4003.0FFF 16/32-bit Timer 0 Table 6-19
0x4003.1000 0x4003.1FFF 16/32-bit Timer 1 Table 6-19
0x4003.2000 0x4003.2FFF 16/32-bit Timer 2 Table 6-19
0x4003.3000 0x4003.3FFF 16/32-bit Timer 3 Table 6-19
0x4003.4000 0x4003.4FFF 16/32-bit Timer 4 Table 6-19
0x4003.5000 0x4003.5FFF 16/32-bit Timer 5 Table 6-19
0x4003.6000 0x4003.7FFF Reserved
0x4003.8000 0x4003.8FFF ADC0 Table 6-7
0x4003.9000 0x4003.9FFF ADC1 Table 6-7
0x4003.A000 0x4003.BFFF Reserved
0x4003.C000 0x4003.CFFF Analog Comparator Table 6-9
0x4003.D000 0x4003.DFFF GPIO Port J Table 6-18
0x4003.E000 0x4003.FFFF Reserved
0x4004.0000 0x4004.0FFF CAN0 Controller Table 6-8
0x4004.1000 0x4004.1FFF CAN1 Controller Table 6-8
0x4004.2000 0x4004.FFFF Reserved
0x4005.0000 0x4005.0FFF USB Table 6-33
0x4005.1000 0x4005.7FFF Reserved
0x4005.8000 0x4005.8FFF GPIO Port A (AHB aperture) Table 6-18
0x4005.9000 0x4005.9FFF GPIO Port B (AHB aperture) Table 6-18
0x4005.A000 0x4005.AFFF GPIO Port C (AHB aperture) Table 6-18
0x4005.B000 0x4005.BFFF GPIO Port D (AHB aperture) Table 6-18
0x4005.C000 0x4005.CFFF GPIO Port E (AHB aperture) Table 6-18
0x4005.D000 0x4005.DFFF GPIO Port F (AHB aperture) Table 6-18
0x4005.E000 0x4005.EFFF GPIO Port G (AHB aperture) Table 6-18
0x4005.F000 0x4005.FFFF GPIO Port H (AHB aperture) Table 6-18
0x4006.0000 0x4006.0FFF GPIO Port J (AHB aperture) Table 6-18
0x4006.1000 0x4006.1FFF GPIO Port K (AHB aperture) Table 6-18
0x4006.2000 0x4006.2FFF GPIO Port L (AHB aperture) Table 6-18
0x4006.3000 0x4006.3FFF GPIO Port M (AHB aperture) Table 6-18
0x4006.4000 0x4006.4FFF GPIO Port N (AHB aperture) Table 6-18
0x4006.5000 0x4006.5FFF GPIO Port P (AHB aperture) Table 6-18
0x4006.6000 0x4006.6FFF GPIO Port Q (AHB aperture) Table 6-18
0x4006.7000 0x4006.7FFF GPIO Port R (AHB aperture) Table 6-18
0x4006.8000 0x4006.8FFF GPIO Port S (AHB aperture) Table 6-18
0x4006.9000 0x4006.9FFF GPIO Port T (AHB aperture) Table 6-18
0x4006.A000 0x400A.EFFF Reserved
0x400A.F000 0x400A.FFFF EEPROM and Key Locker Table 6-13
0x400B.0000 0x400B.5FFF Reserved
0x400B.6000 0x400B.6FFF 1-Wire Master Table 6-4
0x400B.7000 0x400B.7FFF Reserved
0x400B.8000 0x400B.8FFF I2C 8 Table 6-21
0x400B.9000 0x400B.9FFF I2C 9 Table 6-21
0x400B.A000 0x400B.FFFF Reserved
0x400C.0000 0x400C.0FFF I2C 4 Table 6-21
0x400C.1000 0x400C.1FFF I2C 5 Table 6-21
0x400C.2000 0x400C.2FFF I2C 6 Table 6-21
0x400C.3000 0x400C.3FFF I2C 7 Table 6-21
0x400C.4000 0x400C.FFFF Reserved
0x400D.0000 0x400D.0FFF EPI0 Table 6-14
0x400D.1000 0x400D.FFFF Reserved
0x400E.0000 0x400E.0FFF 16/32-bit Timer 6 Table 6-19
0x400E.1000 0x400E.1FFF 16/32-bit Timer 7 Table 6-19
0x400E.2000 0x400E.BFFF Reserved
0x400E.C000 0x400E.CFFF Ethernet Controller Table 6-15
0x400E.D000 0x400F.8FFF Reserved
0x400F.9000 0x400F.9FFF System Exception Table 6-31
0x400F.A000 0x400F.BFFF Reserved
0x400F.C000 0x400F.CFFF Hibernation Table 6-20
0x400F.D000 0x400F.DFFF Flash Memory Control Table 6-17
0x400F.E000 0x400F.EFFF System Control Table 6-30
0x400F.F000 0x400F.FFFF µDMA Table 6-23
0x4010.0000 0x41FF.FFFF Reserved
0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
0x4400.0000 0x4402.FFFF Reserved
0x4403.0000 0x4403.0FFF CRC and Cryptographic Control Table 6-10
0x4403.1000 0x4403.1FFF Reserved (4KB)
0x4403.2000 0x4403.3FFF Reserved (8KB)
0x4403.4000 0x4403.5FFF SHA/MD5 Table 6-28
0x4403.6000 0x4403.7FFF AES Table 6-5, Table 6-6
0x4403.8000 0x4403.9FFF DES Table 6-11, Table 6-12
0x4403.A000 0x4403.EFFF Reserved
0x4403.F000 0x4403.FFFF Reserved (4KB)
0x4404.0000 0x4404.FFFF Reserved (64KB)
0x4405.0000 0x4405.0FFF LCD Table 6-22
0x4405.1000 0x4405.3FFF Reserved
0x4405.4000 0x4405.4FFF EPHY 0 Table 6-16
0x4405.5000 0x5FFF.FFFF Reserved
0x6000.0000 0xDFFF.FFFF EPI0 Mapped Peripheral and RAM Table 6-14

Table 6-4 1-Wire Master Registers

OFFSETACRONYMREGISTER NAME
0x0 ONEWIRECS 1-Wire Control and Status
0x4 ONEWIRETIM 1-Wire Timing Override
0x8 ONEWIREDATW 1-Wire Data Write
0xC ONEWIREDATR 1-Wire Data Read
0x100 ONEWIREIM 1-Wire Interrupt Mask
0x104 ONEWIRERIS 1-Wire Raw Interrupt Status
0x108 ONEWIREMIS 1-Wire Masked Interrupt Status
0x10C ONEWIREICR 1-Wire Interrupt Clear
0x120 ONEWIREDMA 1-Wire µDMA Control
0xFC0 ONEWIREPP 1-Wire Peripheral Properties

Table 6-5 AES Registers

OFFSETACRONYMREGISTER NAME
0x00C AES_KEY2_5 AES Key 2_5
0x010 AES_KEY2_2 AES Key 2_2
0x014 AES_KEY2_3 AES Key 2_3
0x018 AES_KEY2_0 AES Key 2_0
0x01C AES_KEY2_1 AES Key 2_1
0x020 AES_KEY1_6 AES Key 1_6
0x024 AES_KEY1_7 AES Key 1_7
0x028 AES_KEY1_4 AES Key 1_4
0x02C AES_KEY1_5 AES Key 1_5
0x030 AES_KEY1_2 AES Key 1_2
0x034 AES_KEY1_3 AES Key 1_3
0x038 AES_KEY1_0 AES Key 1_0
0x03C AES_KEY1_1 AES Key 1_1
0x40 to 0x4C AES_IV_IN_0 to AES_IV_IN_3 AES Initialization Vector Input 0 to AES Initialization Vector Input 3
0x50 AES_CTRL AES Control
0x54 to 0x58 AES_C_LENGTH_0 to AES_C_LENGTH_1 AES Crypto Data Length 0 to AES Crypto Data Length 1
0x5C AES_AUTH_LENGTH AES Authentication Data Length
0x60 to 0x6C AES_DATA_IN_0 to AES_DATA_IN_3 AES Data R/W Plaintext/Ciphertext 0 to AES Data R/W Plaintext/Ciphertext 3
0x70 to 0x7C AES_TAG_OUT_0 to AES_TAG_OUT_3 AES Hash Tag Out 0 to AES Hash Tag Out 3
0x80 AES_REVISION AES IP Revision Identifier
0x84 AES_SYSCONFIG AES System Configuration
0x88 AES_SYSSTATUS AES System Status
0x8C AES_IRQSTATUS AES Interrupt Status
0x90 AES_IRQENABLE AES Interrupt Enable
0x94 AES_DIRTYBITS AES Dirty Bits

Table 6-6 AES µDMA Registers

OFFSETACRONYMREGISTER NAME
0x20 AES_DMAIM AES DMA Interrupt Mask
0x24 AES_DMARIS AES DMA Raw Interrupt Status
0x28 AES_DMAMIS AES DMA Masked Interrupt Status
0x2C AES_DMAIC AES DMA Interrupt Clear

Table 6-7 ADC Registers

OFFSETACRONYMREGISTER NAME
0x0 ADCACTSS ADC Active Sample Sequencer
0x4 ADCRIS ADC Raw Interrupt Status
0x8 ADCIM ADC Interrupt Mask
0xC ADCISC ADC Interrupt Status and Clear
0x10 ADCOSTAT ADC Overflow Status
0x14 ADCEMUX ADC Event Multiplexer Select
0x18 ADCUSTAT ADC Underflow Status
0x1C ADCTSSEL ADC Trigger Source Select
0x20 ADCSSPRI ADC Sample Sequencer Priority
0x24 ADCSPC ADC Sample Phase Control
0x28 ADCPSSI ADC Processor Sample Sequence Initiate
0x30 ADCSAC ADC Sample Averaging Control
0x34 ADCDCISC ADC Digital Comparator Interrupt Status and Clear
0x38 ADCCTL ADC Control
0x40 ADCSSMUX0 ADC Sample Sequence Input Multiplexer Select 0
0x44 ADCSSCTL0 ADC Sample Sequence Control 0
0x48 ADCSSFIFO0 ADC Sample Sequence Result FIFO 0
0x4C ADCSSFSTAT0 ADC Sample Sequence FIFO 0 Status
0x50 ADCSSOP0 ADC Sample Sequence 0 Operation
0x54 ADCSSDC0 ADC Sample Sequence 0 Digital Comparator Select
0x58 ADCSSEMUX0 ADC Sample Sequence Extended Input Multiplexer Select 0
0x5C ADCSSTSH0 ADC Sample Sequence 0 Sample and Hold Time
0x60 ADCSSMUX1 ADC Sample Sequence Input Multiplexer Select 1
0x64 ADCSSCTL1 ADC Sample Sequence Control 1
0x068 ADCSSFIFO1 ADC Sample Sequence Result FIFO 1
0x06C ADCSSFSTAT1 ADC Sample Sequence FIFO 1 Status
0x70 ADCSSOP1 ADC Sample Sequence 1 Operation
0x74 ADCSSDC1 ADC Sample Sequence 1 Digital Comparator Select
0x78 ADCSSEMUX1 ADC Sample Sequence Extended Input Multiplexer Select 1
0x7C ADCSSTSH1 ADC Sample Sequence 1 Sample and Hold Time
0x080 ADCSSMUX2 ADC Sample Sequence Input Multiplexer Select 2
0x084 ADCSSCTL2 ADC Sample Sequence Control 2
0x088 ADCSSFIFO2 ADC Sample Sequence Result FIFO 2
0x08C ADCSSFSTAT2 ADC Sample Sequence FIFO 2 Status
0x090 ADCSSOP2 ADC Sample Sequence 2 Operation
0x094 ADCSSDC2 ADC Sample Sequence 2 Digital Comparator Select
0x098 ADCSSEMUX2 ADC Sample Sequence Extended Input Multiplexer Select 2
0x09C ADCSSTSH2 ADC Sample Sequence 2 Sample and Hold Time
0xA0 ADCSSMUX3 ADC Sample Sequence Input Multiplexer Select 3
0xA4 ADCSSCTL3 ADC Sample Sequence Control 3
0x0A8 ADCSSFIFO3 ADC Sample Sequence Result FIFO 3
0x0AC ADCSSFSTAT3 ADC Sample Sequence FIFO 3 Status
0xB0 ADCSSOP3 ADC Sample Sequence 3 Operation
0xB4 ADCSSDC3 ADC Sample Sequence 3 Digital Comparator Select
0xB8 ADCSSEMUX3 ADC Sample Sequence Extended Input Multiplexer Select 3
0xBC ADCSSTSH3 ADC Sample Sequence 3 Sample and Hold Time
0xD00 ADCDCRIC ADC Digital Comparator Reset Initial Conditions
0xE00 to 0xE1C ADCDCCTL0 to ADCDCCTL7 ADC Digital Comparator Control 0 to ADC Digital Comparator Control 7
0xE40 to 0xE5C ADCDCCMP0 to ADCDCCMP7 ADC Digital Comparator Range 0 to ADC Digital Comparator Range 7
0xFC0 ADCPP ADC Peripheral Properties
0xFC4 ADCPC ADC Peripheral Configuration
0xFC8 ADCCC ADC Clock Configuration

Table 6-8 CAN Registers

OFFSETACRONYMREGISTER NAME
0x0 CANCTL CAN Control
0x4 CANSTS CAN Status
0x8 CANERR CAN Error Counter
0xC CANBIT CAN Bit Timing
0x10 CANINT CAN Interrupt
0x14 CANTST CAN Test
0x18 CANBRPE CAN Baud Rate Prescaler Extension
0x20 CANIF1CRQ CAN IF1 Command Request
0x24 CANIF1CMSK CAN IF1 Command Mask
0x28 CANIF1MSK1 CAN IF1 Mask 1
0x2C CANIF1MSK2 CAN IF1 Mask 2
0x30 CANIF1ARB1 CAN IF1 Arbitration 1
0x34 CANIF1ARB2 CAN IF1 Arbitration 2
0x38 CANIF1MCTL CAN IF1 Message Control
0x3C CANIF1DA1 CAN IF1 Data A1
0x40 CANIF1DA2 CAN IF1 Data A2
0x44 CANIF1DB1 CAN IF1 Data B1
0x48 CANIF1DB2 CAN IF1 Data B2
0x80 CANIF2CRQ CAN IF2 Command Request
0x84 CANIF2CMSK CAN IF2 Command Mask
0x88 CANIF2MSK1 CAN IF2 Mask 1
0x8C CANIF2MSK2 CAN IF2 Mask 2
0x90 CANIF2ARB1 CAN IF2 Arbitration 1
0x94 CANIF2ARB2 CAN IF2 Arbitration 2
0x98 CANIF2MCTL CAN IF2 Message Control
0x9C CANIF2DA1 CAN IF2 Data A1
0xA0 CANIF2DA2 CAN IF2 Data A2
0xA4 CANIF2DB1 CAN IF2 Data B1
0xA8 CANIF2DB2 CAN IF2 Data B2
0x100 CANTXRQ1 CAN Transmission Request 1
0x104 CANTXRQ2 CAN Transmission Request 2
0x120 CANNWDA1 CAN New Data 1
0x124 CANNWDA2 CAN New Data 2
0x140 CANMSG1INT CAN Message 1 Interrupt Pending
0x144 CANMSG2INT CAN Message 2 Interrupt Pending
0x160 CANMSG1VAL CAN Message 1 Valid
0x164 CANMSG2VAL CAN Message 2 Valid

Table 6-9 Comparator Registers

OFFSETACRONYMREGISTER NAME
0x0 ACMIS Analog Comparator Masked Interrupt Status
0x4 ACRIS Analog Comparator Raw Interrupt Status
0x8 ACINTEN Analog Comparator Interrupt Enable
0x10 ACREFCTL Analog Comparator Reference Voltage Control
0x20 ACSTAT0 Analog Comparator Status 0
0x24 ACCTL0 Analog Comparator Control 0
0x40 ACSTAT1 Analog Comparator Status 1
0x44 ACCTL1 Analog Comparator Control 1
0x60 ACSTAT2 Analog Comparator Status 2
0x64 ACCTL2 Analog Comparator Control 2
0xFC0 ACMPPP Analog Comparator Peripheral Properties

Table 6-10 CRC Registers

OFFSETACRONYMREGISTER NAME
400h CRCCTRL CRC Control
410h CRCSEED CRC SEED/Context
414h CRCDIN CRC Data Input
418h CRCRSLTPP CRC Post Processing Result

Table 6-11 DES Registers

OFFSETACRONYMREGISTER NAME
0x00 DES_KEY3_L DES Key 3 LSW for 192-Bit Key
0x04 DES_KEY3_H DES Key 3 MSW for 192-Bit Key
0x08 DES_KEY2_L DES Key 2 LSW for 128-Bit Key
0x0C DES_KEY2_H DES Key 2 MSW for 128-Bit Key
0x10 DES_KEY1_L DES Key 1 LSW for 64-Bit Key
0x14 DES_KEY1_H DES Key 1 MSW for 64-Bit Key
0x18 DES_IV_L DES Initialization Vector
0x1C DES_IV_H DES Initialization Vector
0x20 DES_CTRL DES Control
0x24 DES_LENGTH DES Cryptographic Data Length
0x28 DES_DATA_L DES LSW Data RW
0x2C DES_DATA_H DES MSW Data RW
0x30 DES_REVISION DES Revision Number
0x34 DES_SYSCONFIG DES System Configuration
0x38 DES_SYSSTATUS DES System Status
0x3C DES_IRQSTATUS DES Interrupt Status
0x40 DES_IRQENABLE DES Interrupt Enable
0x44 DES_DIRTYBITS DES Dirty Bits

Table 6-12 DES µDMA Registers

OFFSETACRONYMREGISTER NAME
0x30 DES_DMAIM DES DMA Interrupt Mask
0x34 DES_DMARIS DES DMA Raw Interrupt Status
0x38 DES_DMAMIS DES DMA Masked Interrupt Status
0x3C DES_DMAIC DES DMA Interrupt Clear

Table 6-13 EEPROM Registers

OFFSETACRONYMREGISTER NAME
0x0 EESIZE EEPROM Size Information
0x4 EEBLOCK EEPROM Current Block
0x8 EEOFFSET EEPROM Current Offset
0x10 EERDWR EEPROM Read-Write
0x14 EERDWRINC EEPROM Read-Write with Increment
0x18 EEDONE EEPROM Done Status
0x1C EESUPP EEPROM Support Control and Status
0x20 EEUNLOCK EEPROM Unlock
0x30 EEPROT EEPROM Protection
0x34 to 0x3C EEPASS0 to EEPASS2 EEPROM Password 0 to EEPROM Password 2
0x40 EEINT EEPROM Interrupt
0x50 EEHIDE0 EEPROM Block Hide 0
0x54 EEHIDE1 EEPROM Block Hide 1
0x58 EEHIDE2 EEPROM Block Hide 2
0x80 EEDBGME EEPROM Debug Mass Erase
0xFC0 EEPROMPP EEPROM Peripheral Properties

Table 6-14 EPI Registers

OFFSETACRONYMREGISTER NAME
0x000 EPICFG EPI Configuration
0x004 EPIBAUD EPI Main Baud Rate
0x008 EPIBAUD2 EPI Main Baud Rate
0x010 EPISDRAMCFG EPI SDRAM Configuration
0x010 EPIHB8CFG EPI Host-Bus 8 Configuration
0x010 EPIHB16CFG EPI Host-Bus 16 Configuration
0x010 EPIGPCFG EPI General-Purpose Configuration
0x014 EPIHB8CFG2 EPI Host-Bus 8 Configuration 2
0x014 EPIHB16CFG2 EPI Host-Bus 16 Configuration 2
0x01C EPIADDRMAP EPI Address Map
0x020 EPIRSIZE0 EPI Read Size 0
0x024 EPIRADDR0 EPI Read Address 0
0x028 EPIRPSTD0 EPI Non-Blocking Read Data 0
0x030 EPIRSIZE1 EPI Read Size 1
0x034 EPIRADDR1 EPI Read Address 1
0x038 EPIRPSTD1 EPI Non-Blocking Read Data 1
0x060 EPISTAT EPI Status
0x06C EPIRFIFOCNT EPI Read FIFO Count
0x70 to 0x8C EPIREADFIFO0 to EPIREADFIFO7 EPI Read FIFO 0 to EPI Read FIFO 7
0x200 EPIFIFOLVL EPI FIFO Level Selects
0x24 EPIWFIFOCNT EPI Write FIFO Count
0x28 EPIDMATXCNT EPI DMA Transmit Count
0x210 EPIIM EPI Interrupt Mask
0x214 EPIRIS EPI Raw Interrupt Status
0x218 EPIMIS EPI Masked Interrupt Status
0x21C EPIEISC EPI Error and Interrupt Status and Clear
0x308 EPIHB8CFG3 EPI Host-Bus 8 Configuration 3
0x308 EPIHB16CFG3 EPI Host-Bus 16 Configuration 3
0x30C EPIHB8CFG4 EPI Host-Bus 8 Configuration 4
0x30C EPIHB16CFG4 EPI Host-Bus 16 Configuration 4
0x310 EPIHB8TIME EPI Host-Bus 8 Timing Extension
0x310 EPIHB16TIME EPI Host-Bus 16 Timing Extension
0x314 EPIHB8TIME2 EPI Host-Bus 8 Timing Extension
0x314 EPIHB16TIME2 EPI Host-Bus 16 Timing Extension
0x318 EPIHB8TIME3 EPI Host-Bus 8 Timing Extension
0x318 EPIHB16TIME3 EPI Host-Bus 16 Timing Extension
0x31C EPIHB8TIME4 EPI Host-Bus 8 Timing Extension
0x31C EPIHB16TIME4 EPI Host-Bus 16 Timing Extension
0x360 EPIHBPSRAM EPI Host-Bus PSRAM

Table 6-15 Ethernet MAC (EMAC) Registers

OFFSETACRONYMREGISTER NAME
0x0 EMACCFG Ethernet MAC Configuration
0x4 EMACFRAMEFLTR Ethernet MAC Frame Filter
0x8 EMACHASHTBLH Ethernet MAC Hash Table High
0xC EMACHASHTBLL Ethernet MAC Hash Table Low
0x10 EMACMIIADDR Ethernet MAC MII Address
0x14 EMACMIIDATA Ethernet MAC MII Data Register
0x18 EMACFLOWCTL Ethernet MAC Flow Control
0x1C EMACVLANTG Ethernet MAC VLAN Tag
0x24 EMACSTATUS Ethernet MAC Status
0x28 EMACRWUFF Ethernet MAC Remote Wake-Up Frame Filter
0x2C EMACPMTCTLSTAT Ethernet MAC PMT Control and Status
0x30 EMACLPICTLSTAT LPI Control and Status
0x34 EMACLPITIMERCTRL LPI Timers Control
0x38 EMACRIS Ethernet MAC Raw Interrupt Status
0x3C EMACIM Ethernet MAC Interrupt Mask
0x40 EMACADDR0H Ethernet MAC Address 0 High
0x44 EMACADDR0L Ethernet MAC Address 0 Low Register
0x48 EMACADDR1H Ethernet MAC Address 1 High
0x4C EMACADDR1L Ethernet MAC Address 1 Low
0x50 EMACADDR2H Ethernet MAC Address 2 High
0x54 EMACADDR2L Ethernet MAC Address 2 Low
0x58 EMACADDR3H Ethernet MAC Address 3 High
0x5C EMACADDR3L Ethernet MAC Address 3 Low
0xDC EMACWDOGTO Ethernet MAC Watchdog Time-out
0x100 EMACMMCCTRL Ethernet MAC MMC Control
0x104 EMACMMCRXRIS Ethernet MAC MMC Receive Raw Interrupt Status
0x108 EMACMMCTXRIS Ethernet MAC MMC Transmit Raw Interrupt Status
0x10C EMACMMCRXIM Ethernet MAC MMC Receive Interrupt Mask
0x110 EMACMMCTXIM Ethernet MAC MMC Transmit Interrupt Mask
0x118 EMACTXCNTGB Ethernet MAC Transmit Frame Count for Good and Bad Frames
0x14C EMACTXCNTSCOL Ethernet MAC Transmit Frame Count for Frames Transmitted After Single Collision
0x150 EMACTXCNTMCOL Ethernet MAC Transmit Frame Count for Frames Transmitted After Multiple Collisions
0x164 EMACTXOCTCNTG Ethernet MAC Transmit Octet Count Good
0x180 EMACRXCNTGB Ethernet MAC Receive Frame Count for Good and Bad Frames
0x194 EMACRXCNTCRCERR Ethernet MAC Receive Frame Count for CRC Error Frames
0x198 EMACRXCNTALGNERR Ethernet MAC Receive Frame Count for Alignment Error Frames
0x1C4 EMACRXCNTGUNI Ethernet MAC Receive Frame Count for Good Unicast Frames
0x584 EMACVLNINCREP Ethernet MAC VLAN Tag Inclusion or Replacement
0x588 EMACVLANHASH Ethernet MAC VLAN Hash Table
0x700 EMACTIMSTCTRL Ethernet MAC Timestamp Control
0x704 EMACSUBSECINC Ethernet MAC Sub-Second Increment
0x708 EMACTIMSEC Ethernet MAC System Time - Seconds
0x70C EMACTIMNANO Ethernet MAC System Time - Nanoseconds
0x710 EMACTIMSECU Ethernet MAC System Time - Seconds Update
0x714 EMACTIMNANOU Ethernet MAC System Time - Nanoseconds Update
0x718 EMACTIMADD Ethernet MAC Timestamp Addend
0x71C EMACTARGSEC Ethernet MAC Target Time Seconds
0x720 EMACTARGNANO Ethernet MAC Target Time Nanoseconds
0x724 EMACHWORDSEC Ethernet MAC System Time-Higher Word Seconds
0x728 EMACTIMSTAT Ethernet MAC Timestamp Status
0x72C EMACPPSCTRL Ethernet MAC PPS Control
0x760 EMACPPS0INTVL Ethernet MAC PPS0 Interval
0x764 EMACPPS0WIDTH Ethernet MAC PPS0 Width
0xC00 EMACDMABUSMOD Ethernet MAC DMA Bus Mode
0xC04 EMACTXPOLLD Ethernet MAC Transmit Poll Demand
0xC08 EMACRXPOLLD Ethernet MAC Receive Poll Demand
0xC0C EMACRXDLADDR Ethernet MAC Receive Descriptor List Address
0xC10 EMACTXDLADDR Ethernet MAC Transmit Descriptor List Address
0xC14 EMACDMARIS Ethernet MAC DMA Interrupt Status
0xC18 EMACDMAOPMODE Ethernet MAC DMA Operation Mode
0xC1C EMACDMAIM Ethernet MAC DMA Interrupt Mask Register
0xC20 EMACMFBOC Ethernet MAC Missed Frame and Buffer Overflow Counter
0xC24 EMACRXINTWDT Ethernet MAC Receive Interrupt Watchdog Timer
0xC48 EMACHOSTXDESC Ethernet MAC Current Host Transmit Descriptor
0xC4C EMACHOSRXDESC Ethernet MAC Current Host Receive Descriptor
0xC50 EMACHOSTXBA Ethernet MAC Current Host Transmit Buffer Address
0xC54 EMACHOSRXBA Ethernet MAC Current Host Receive Buffer Address
0xFC0 EMACPP Ethernet MAC Peripheral Property Register
0xFC4 EMACPC Ethernet MAC Peripheral Configuration
0xFC8 EMACCC Ethernet MAC Clock Configuration
0xFD0 EPHYRIS Ethernet PHY Raw Interrupt Status
0xFD4 EPHYIM Ethernet PHY Interrupt Mask
0xFD8 EPHYMISC Ethernet PHY Masked Interrupt Status and Clear

Table 6-16 Ethernet MII Management (EPHY) Registers (Accessed Through the EMACMIIADDR Register)

ADDRESSACRONYMREGISTER NAME
0x00 EPHYBMCR Ethernet PHY Basic Mode Control - MR0
0x01 EPHYBMSR Ethernet PHY Basic Mode Status - MR1
0x02 EPHYID1 Ethernet PHY Identifier Register 1 - MR2
0x03 EPHYID2 Ethernet PHY Identifier Register 2 - MR3
0x04 EPHYANA Ethernet PHY Auto-Negotiation Advertisement - MR4
0x05 EPHYANLPA Ethernet PHY Auto-Negotiation Link Partner Ability -MR5
0x06 EPHYANER Ethernet PHY Auto-Negotiation Expansion - MR6
0x07 EPHYANNPTR Ethernet PHY Auto-Negotiation Next Page TX - MR7
0x08 EPHYANLNPTR Ethernet PHY Auto-Negotiation Link Partner Ability Next Page - MR8
0x09 EPHYCFG1 Ethernet PHY Configuration 1 - MR9
0x0A EPHYCFG2 Ethernet PHY Configuration 2 - MR10
0x0B EPHYCFG3 Ethernet PHY Configuration 3 - MR11
0x0D EPHYREGCTL Ethernet PHY Register Control - MR13
0x0E EPHYADDAR Ethernet PHY Address or Data - MR14
0x10 EPHYSTS Ethernet PHY Status - MR16
0x11 EPHYSCR Ethernet PHY Specific Control - MR17
0x12 EPHYMISR1 Ethernet PHY MII Interrupt Status 1 - MR18
0x13 EPHYMISR2 Ethernet PHY MII Interrupt Status 2 - MR19
0x14 EPHYFCSCR Ethernet PHY False Carrier Sense Counter - MR20
0x15 EPHYRXERCNT Ethernet PHY Receive Error Count - MR21
0x16 EPHYBISTCR Ethernet PHY BIST Control - MR22
0x18 EPHYLEDCR Ethernet PHY LED Control - MR24
0x19 EPHYCTL Ethernet PHY Control - MR25
0x1A EPHY10BTSC Ethernet PHY 10Base-T Status/Control - MR26
0x1B EPHYBICSR1 Ethernet PHY BIST Control and Status 1 - MR27
0x1C EPHYBICSR2 Ethernet PHY BIST Control and Status 2 - MR28
0x1E EPHYCDCR Ethernet PHY Cable Diagnostic Control - MR30
0x1F EPHYRCR Ethernet PHY Reset Control - MR31
0x25 EPHYLEDCFG Ethernet PHY LED Configuration - MR37

Table 6-17 Flash Registers

OFFSETACRONYMREGISTER NAME
0x0 FMA Flash Memory Address
0x4 FMD Flash Memory Data
0x8 FMC Flash Memory Control
0xC FCRIS Flash Controller Raw Interrupt Status
0x10 FCIM Flash Controller Interrupt Mask
0x14 FCMISC Flash Controller Masked Interrupt Status and Clear
0x20 FMC2 Flash Memory Control 2
0x30 FWBVAL Flash Write Buffer Valid
0x3C FLPEKEY Flash Program/Erase Key
0x100 to 0x17C FWB0 to FWB31 Flash Write Buffer 0 to Flash Write Buffer 32
0xFC0 FLASHPP Flash Peripheral Properties
0xFC4 SSIZE SRAM Size
0xFC8 FLASHCONF Flash Configuration Register
0xFCC ROMSWMAP ROM Third-Party Software
0xFD0 FLASHDMASZ Flash DMA Address Size
0xFD4 FLASHDMAST Flash DMA Starting Address

Table 6-18 GPIO Registers

OFFSETACRONYMREGISTER NAME
0x0 GPIODATA GPIO Data
0x400 GPIODIR GPIO Direction
0x404 GPIOIS GPIO Interrupt Sense
0x408 GPIOIBE GPIO Interrupt Both Edges
0x40C GPIOIEV GPIO Interrupt Event
0x410 GPIOIM GPIO Interrupt Mask
0x414 GPIORIS GPIO Raw Interrupt Status
0x418 GPIOMIS GPIO Masked Interrupt Status
0x41C GPIOICR GPIO Interrupt Clear
0x420 GPIOAFSEL GPIO Alternate Function Select
0x500 GPIODR2R GPIO 2-mA Drive Select
0x504 GPIODR4R GPIO 4-mA Drive Select
0x508 GPIODR8R GPIO 8-mA Drive Select
0x50C GPIOODR GPIO Open Drain Select
0x510 GPIOPUR GPIO Pullup Select
0x514 GPIOPDR GPIO Pulldown Select
0x518 GPIOSLR GPIO Slew Rate Control Select
0x51C GPIODEN GPIO Digital Enable
0x520 GPIOLOCK GPIO Lock
0x524 GPIOCR GPIO Commit
0x528 GPIOAMSEL GPIO Analog Mode Select
0x52C GPIOPCTL GPIO Port Control
0x530 GPIOADCCTL GPIO ADC Control
0x534 GPIODMACTL GPIO DMA Control
0x538 GPIOSI GPIO Select Interrupt
0x53C GPIODR12R GPIO 12-mA Drive Select
0x540 GPIOWAKEPEN GPIO Wake Pin Enable
0x544 GPIOWAKELVL GPIO Wake Level
0x548 GPIOWAKESTAT GPIO Wake Status
0xFC0 GPIOPP GPIO Peripheral Property
0xFC4 GPIOPC GPIO Peripheral Configuration
0xFD0 GPIOPeriphID4 GPIO Peripheral Identification 4
0xFD4 GPIOPeriphID5 GPIO Peripheral Identification 5
0xFD8 GPIOPeriphID6 GPIO Peripheral Identification 6
0xFDC GPIOPeriphID7 GPIO Peripheral Identification 7
0xFE0 GPIOPeriphID0 GPIO Peripheral Identification 0
0xFE4 GPIOPeriphID1 GPIO Peripheral Identification 1
0xFE8 GPIOPeriphID2 GPIO Peripheral Identification 2
0xFEC GPIOPeriphID3 GPIO Peripheral Identification 3
0xFF0 GPIOPCellID0 GPIO PrimeCell Identification 0
0xFF4 GPIOPCellID1 GPIO PrimeCell Identification 1
0xFF8 GPIOPCellID2 GPIO PrimeCell Identification 2
0xFFC GPIOPCellID3 GPIO PrimeCell Identification 3

Table 6-19 GPTM Registers

OFFSETACRONYMREGISTER NAME
0x0 GPTMCFG GPTM Configuration
0x4 GPTMTAMR GPTM Timer A Mode
0x8 GPTMTBMR GPTM Timer B Mode
0xC GPTMCTL GPTM Control
0x10 GPTMSYNC GPTM Synchronize
0x18 GPTMIMR GPTM Interrupt Mask
0x1C GPTMRIS GPTM Raw Interrupt Status
0x20 GPTMMIS GPTM Masked Interrupt Status
0x24 GPTMICR GPTM Interrupt Clear
0x28 GPTMTAILR GPTM Timer A Interval Load
0x2C GPTMTBILR GPTM Timer B Interval Load
0x30 GPTMTAMATCHR GPTM Timer A Match
0x34 GPTMTBMATCHR GPTM Timer B Match
0x38 GPTMTAPR GPTM Timer A Prescale
0x3C GPTMTBPR GPTM Timer B Prescale
0x40 GPTMTAPMR GPTM TimerA Prescale Match
0x44 GPTMTBPMR GPTM TimerB Prescale Match
0x48 GPTMTAR GPTM Timer A
0x4C GPTMTBR GPTM Timer B
0x50 GPTMTAV GPTM Timer A Value
0x54 GPTMTBV GPTM Timer B Value
0x58 GPTMRTCPD GPTM RTC Predivide
0x5C GPTMTAPS GPTM Timer A Prescale Snapshot
0x60 GPTMTBPS GPTM Timer B Prescale Snapshot
0x6C GPTMDMAEV GPTM DMA Event
0x70 GPTMADCEV GPTM ADC Event
0xFC0 GPTMPP GPTM Peripheral Properties
0xFC8 GPTMCC GPTM Clock Configuration

Table 6-20 HIB Registers

OFFSETACRONYMREGISTER NAME
0x0 HIBRTCC Hibernation RTC Counter
0x4 HIBRTCM0 Hibernation RTC Match 0
0xC HIBRTCLD Hibernation RTC Load
0x10 HIBCTL Hibernation Control
0x14 HIBIM Hibernation Interrupt Mask
0x18 HIBRIS Hibernation Raw Interrupt Status
0x1C HIBMIS Hibernation Masked Interrupt Status
0x20 HIBIC Hibernation Interrupt Clear
0x24 HIBRTCT Hibernation RTC Trim
0x28 HIBRTCSS Hibernation RTC Sub Seconds
0x2C HIBIO Hibernation IO Configuration
0x30 to 0x6F HIBDATA Hibernation Data
0x300 HIBCALCTL Hibernation Calendar Control
0x310 HIBCAL0 Hibernation Calendar 0
0x314 HIBCAL1 Hibernation Calendar 1
0x320 HIBCALLD0 Hibernation Calendar Load 0
0x324 HIBCALLD1 Hibernation Calendar Load 1
0x330 HIBCALM0 Hibernation Calendar Match 0
0x334 HIBCALM1 Hibernation Calendar Match 1
0x360 HIBLOCK Hibernation Lock
0x400 HIBTPCTL HIB Tamper Control
0x404 HIBTPSTAT HIB Tamper Status
0x410 HIBTPIO HIB Tamper I/O Control
0x4E0 HIBTPLOG0 HIB Tamper Log 0
0x4E4 HIBTPLOG1 HIB Tamper Log 1
0x4E8 HIBTPLOG2 HIB Tamper Log 2
0x4EC HIBTPLOG3 HIB Tamper Log 3
0x4F0 HIBTPLOG4 HIB Tamper Log 4
0x4F4 HIBTPLOG5 HIB Tamper Log 5
0x4F8 HIBTPLOG6 HIB Tamper Log 6
0x4FC HIBTPLOG7 HIB Tamper Log 7
0xFC0 HIBPP Hibernation Peripheral Properties
0xFC8 HIBCC Hibernation Clock Control

Table 6-21 I2C Registers

OFFSETACRONYMREGISTER NAME
0x0 I2CMSA I2C Master Slave Address
0x4 I2CMCS I2C Master Control/Status
0x8 I2CMDR I2C Master Data
0xC I2CMTPR I2C Master Timer Period
0x10 I2CMIMR I2C Master Interrupt Mask
0x14 I2CMRIS I2C Master Raw Interrupt Status
0x18 I2CMMIS I2C Master Masked Interrupt Status
0x1C I2CMICR I2C Master Interrupt Clear
0x20 I2CMCR I2C Master Configuration
0x24 I2CMCLKOCNT I2C Master Clock Low Time-out Count
0x2C I2CMBMON I2C Master Bus Monitor
0x30 I2CMBLEN I2C Master Burst Length
0x34 I2CMBCNT I2C Master Burst Count
0x800 I2CSOAR I2C Slave Own Address
0x804 I2CSCSR I2C Slave Control/Status
0x808 I2CSDR I2C Slave Data
0x80C I2CSIMR I2C Slave Interrupt Mask
0x810 I2CSRIS I2C Slave Raw Interrupt Status
0x814 I2CSMIS I2C Slave Masked Interrupt Status
0x818 I2CSICR I2C Slave Interrupt Clear
0x81C I2CSOAR2 I2C Slave Own Address 2
0x820 I2CSACKCTL I2C Slave ACK Control
0xF00 I2CFIFODATA I2C FIFO Data
0xF04 I2CFIFOCTL I2C FIFO Control
0xF08 I2CFIFOSTATUS I2C FIFO Status
0xFC0 I2CPP I2C Peripheral Properties
0xFC4 I2CPC I2C Peripheral Configuration

Table 6-22 LCD Registers

OFFSETACRONYMREGISTER NAME
0x0 LCDPID LCD PID Register Format
0x4 LCDCTL LCD Control
0xC LCDLIDDCTL LCD LIDD Control
0x10 LIDDCS0CFG LCD LIDD CS0 Configuration
0x14 LIDDCS0ADDR LIDD CS0 Read/Write Address
0x18 LIDDCS0DATA LIDD CS0 Data Read/Write Initiation
0x1C LIDDCS1CFG LIDD CS1 Configuration
0x20 LIDDCS1ADDR LIDD CS1 Address Read/Write Initiation
0x24 LIDDCS1DATA LIDD CS1 Data Read/Write Initiation
0x28 LCDRASTRCTL LCD Raster Control
0x2C LCDRASTRTIM0 LCD Raster Timing 0
0x30 LCDRASTRTIM1 LCD Raster Timing 1
0x34 LCDRASTRTIM2 LCD Raster Timing 2
0x38 LCDRASTRSUBP1 LCD Raster Subpanel Display 1
0x3C LCDRASTRSUBP2 LCD Raster Subpanel Display 2
0x40 LCDDMACTL LCD DMA Control
0x44 LCDDMABAFB0 LCD DMA Frame Buffer 0 Base Address
0x48 LCDDMACAFB0 LCD DMA Frame Buffer 0 Ceiling Address
0x4C LCDDMABAFB1 LCD DMA Frame Buffer 1 Base Address
0x50 LCDDMACAFB1 LCD DMA Frame Buffer 1 Ceiling Address
0x54 LCDSYSCFG LCD System Configuration Register
0x58 LCDRISSET LCD Interrupt Raw Status and Set Register
0x5C LCDMISCLR LCD Interrupt Status and Clear
0x60 LCDIM LCD Interrupt Mask
0x64 LCDIENC LCD Interrupt Enable Clear
0x6C LCDCLKEN LCD Clock Enable
0x70 LCDCLKRESET LCD Clock Resets

Table 6-23 µDMA Registers

OFFSETACRONYMREGISTER NAME
0x0 DMASTAT DMA Status
0x4 DMACFG DMA Configuration
0x8 DMACTLBASE DMA Channel Control Base Pointer
0xC DMAALTBASE DMA Alternate Channel Control Base Pointer
0x10 DMAWAITSTAT DMA Channel Wait-on-Request Status
0x14 DMASWREQ DMA Channel Software Request
0x18 DMAUSEBURSTSET DMA Channel Useburst Set
0x1C DMAUSEBURSTCLR DMA Channel Useburst Clear
0x20 DMAREQMASKSET DMA Channel Request Mask Set
0x24 DMAREQMASKCLR DMA Channel Request Mask Clear
0x28 DMAENASET DMA Channel Enable Set
0x2C DMAENACLR DMA Channel Enable Clear
0x30 DMAALTSET DMA Channel Primary Alternate Set
0x34 DMAALTCLR DMA Channel Primary Alternate Clear
0x38 DMAPRIOSET DMA Channel Priority Set
0x3C DMAPRIOCLR DMA Channel Priority Clear
0x4C DMAERRCLR DMA Bus Error Clear
0x510 DMACHMAP0 DMA Channel Map Select 0
0x514 DMACHMAP1 DMA Channel Map Select 1
0x518 DMACHMAP2 DMA Channel Map Select 2
0x51C DMACHMAP3 DMA Channel Map Select 3
0xFD0 DMAPeriphID4 DMA Peripheral Identification 4
0xFE0 DMAPeriphID0 DMA Peripheral Identification 0
0xFE4 DMAPeriphID1 DMA Peripheral Identification 1
0xFE8 DMAPeriphID2 DMA Peripheral Identification 2
0xFEC DMAPeriphID3 DMA Peripheral Identification 3
0xFF0 DMAPCellID0 DMA PrimeCell Identification 0
0xFF4 DMAPCellID1 DMA PrimeCell Identification 1
0xFF8 DMAPCellID2 DMA PrimeCell Identification 2
0xFFC DMAPCellID3 DMA PrimeCell Identification 3

Table 6-24 µDMA Channel Control Structure Registers

OFFSETACRONYMREGISTER NAME
0x0 DMASRCENDP DMA Channel Source Address End Pointer
0x4 DMADSTENDP DMA Channel Destination Address End Pointer
0x8 DMACHCTL DMA Channel Control Word

Table 6-25 PWM Registers

OFFSETACRONYMREGISTER NAME
0x0 PWMCTL PWM Master Control
0x4 PWMSYNC PWM Time Base Sync
0x8 PWMENABLE PWM Output Enable
0xC PWMINVERT PWM Output Inversion
0x10 PWMFAULT PWM Output Fault
0x14 PWMINTEN PWM Interrupt Enable
0x18 PWMRIS PWM Raw Interrupt Status
0x1C PWMISC PWM Interrupt Status and Clear
0x20 PWMSTATUS PWM Status
0x24 PWMFAULTVAL PWM Fault Condition Value
0x28 PWMENUPD PWM Enable Update
0x40 PWM0CTL PWM0 Control
0x44 PWM0INTEN PWM0 Interrupt and Trigger Enable
0x48 PWM0RIS PWM0 Raw Interrupt Status
0x4C PWM0ISC PWM0 Interrupt Status and Clear
0x50 PWM0LOAD PWM0 Load
0x54 PWM0COUNT PWM0 Counter
0x58 PWM0CMPA PWM0 Compare A
0x5C PWM0CMPB PWM0 Compare B
0x60 PWM0GENA PWM0 Generator A Control
0x64 PWM0GENB PWM0 Generator B Control
0x68 PWM0DBCTL PWM0 Dead-Band Control
0x6C PWM0DBRISE PWM0 Dead-Band Rising-Edge Delay
0x70 PWM0DBFALL PWM0 Dead-Band Falling-Edge-Delay
0x74 PWM0FLTSRC0 PWM0 Fault Source 0
0x78 PWM0FLTSRC1 PWM0 Fault Source 1
0x7C PWM0MINFLTPER PWM0 Minimum Fault Period
0x080 PWM1CTL PWM1 Control
0x084 PWM1INTEN PWM1 Interrupt and Trigger Enable
0x088 PWM1RIS PWM1 Raw Interrupt Status
0x08C PWM1ISC PWM1 Interrupt Status and Clear
0x090 PWM1LOAD PWM1 Load
0x094 PWM1COUNT PWM1 Counter
0x098 PWM1CMPA PWM1 Compare A
0x09C PWM1CMPB PWM1 Compare B
0x0A0 PWM1GENA PWM1 Generator A Control
0x0A4 PWM1GENB PWM1 Generator B Control
0x0A8 PWM1DBCTL PWM1 Dead-Band Control
0x0AC PWM1DBRISE PWM1 Dead-Band Rising-Edge Delay
0x0B0 PWM1DBFALL PWM1 Dead-Band Falling-Edge-Delay
0x0B4 PWM1FLTSRC0 PWM1 Fault Source 0
0x0B8 PWM1FLTSRC1 PWM1 Fault Source 1
0x0BC PWM1MINFLTPER PWM1 Minimum Fault Period
0x0C0 PWM2CTL PWM2 Control
0x0C4 PWM2INTEN PWM2 Interrupt and Trigger Enable
0x0C8 PWM2RIS PWM2 Raw Interrupt Status
0x0CC PWM2ISC PWM2 Interrupt Status and Clear
0x0D0 PWM2LOAD PWM2 Load
0x0D4 PWM2COUNT PWM2 Counter
0x0D8 PWM2CMPA PWM2 Compare A
0x0DC PWM2CMPB PWM2 Compare B
0x0E0 PWM2GENA PWM2 Generator A Control
0x0E4 PWM2GENB PWM2 Generator B Control
0x0E8 PWM2DBCTL PWM2 Dead-Band Control
0x0EC PWM2DBRISE PWM2 Dead-Band Rising-Edge Delay
0x0F0 PWM2DBFALL PWM2 Dead-Band Falling-Edge-Delay
0x0F4 PWM2FLTSRC0 PWM2 Fault Source 0
0x0F8 PWM2FLTSRC1 PWM2 Fault Source 1
0x0FC PWM2MINFLTPER PWM2 Minimum Fault Period
0x100 PWM3CTL PWM3 Control
0x104 PWM3INTEN PWM3 Interrupt and Trigger Enable
0x108 PWM3RIS PWM3 Raw Interrupt Status
0x10C PWM3ISC PWM3 Interrupt Status and Clear
0x110 PWM3LOAD PWM3 Load
0x114 PWM3COUNT PWM3 Counter
0x118 PWM3CMPA PWM3 Compare A
0x11C PWM3CMPB PWM3 Compare B
0x120 PWM3GENA PWM3 Generator A Control
0x124 PWM3GENB PWM3 Generator B Control
0x128 PWM3DBCTL PWM3 Dead-Band Control
0x12C PWM3DBRISE PWM3 Dead-Band Rising-Edge Delay
0x130 PWM3DBFALL PWM3 Dead-Band Falling-Edge-Delay
0x134 PWM3FLTSRC0 PWM3 Fault Source 0
0x138 PWM3FLTSRC1 PWM3 Fault Source 1
0x13C PWM3MINFLTPER PWM3 Minimum Fault Period
0x800 PWM0FLTSEN PWM0 Fault Pin Logic Sense
0x804 PWM0FLTSTAT0 PWM0 Fault Status 0
0x808 PWM0FLTSTAT1 PWM0 Fault Status 1
0x880 PWM1FLTSEN PWM1 Fault Pin Logic Sense
0x884 PWM1FLTSTAT0 PWM1 Fault Status 0
0x888 PWM1FLTSTAT1 PWM1 Fault Status 1
0x900 PWM2FLTSEN PWM2 Fault Pin Logic Sense
0x904 PWM2FLTSTAT0 PWM2 Fault Status 0
0x908 PWM2FLTSTAT1 PWM2 Fault Status 1
0x980 PWM3FLTSEN PWM3 Fault Pin Logic Sense
0x984 PWM3FLTSTAT0 PWM3 Fault Status 0
0x988 PWM3FLTSTAT1 PWM3 Fault Status 1
0xFC0 PWMPP PWM Peripheral Properties
0xFC8 PWMCC PWM Clock Configuration

Table 6-26 QEI Registers

OFFSETACRONYMREGISTER NAME
0x0 QEICTL QEI Control
0x4 QEISTAT QEI Status
0x8 QEIPOS QEI Position
0xC QEIMAXPOS QEI Maximum Position
0x10 QEILOAD QEI Timer Load
0x14 QEITIME QEI Timer
0x18 QEICOUNT QEI Velocity Counter
0x1C QEISPEED QEI Velocity
0x20 QEIINTEN QEI Interrupt Enable
0x24 QEIRIS QEI Raw Interrupt Status
0x28 QEIISC QEI Interrupt Status and Clear

Table 6-27 QSSI Registers

OFFSETACRONYMREGISTER NAME
0x0 SSICR0 QSSI Control 0
0x4 SSICR1 QSSI Control 1
0x8 SSIDR QSSI Data
0xC SSISR QSSI Status
0x10 SSICPSR QSSI Clock Prescale
0x14 SSIIM QSSI Interrupt Mask
0x18 SSIRIS QSSI Raw Interrupt Status
0x1C SSIMIS QSSI Masked Interrupt Status
0x20 SSIICR QSSI Interrupt Clear
0x24 SSIDMACTL QSSI DMA Control
0xFC0 SSIPP QSSI Peripheral Properties
0xFC8 SSICC QSSI Clock Configuration
0xFD0 SSIPeriphID4 QSSI Peripheral Identification 4
0xFD4 SSIPeriphID5 QSSI Peripheral Identification 5
0xFD8 SSIPeriphID6 QSSI Peripheral Identification 6
0xFDC SSIPeriphID7 QSSI Peripheral Identification 7
0xFE0 SSIPeriphID0 QSSI Peripheral Identification 0
0xFE4 SSIPeriphID1 QSSI Peripheral Identification 1
0xFE8 SSIPeriphID2 QSSI Peripheral Identification 2
0xFEC SSIPeriphID3 QSSI Peripheral Identification 3
0xFF0 SSIPCellID0 QSSI PrimeCell Identification 0
0xFF4 SSIPCellID1 QSSI PrimeCell Identification 1
0xFF8 SSIPCellID2 QSSI PrimeCell Identification 2
0xFFC SSIPCellID3 QSSI PrimeCell Identification 3

Table 6-28 SHA/MD5 Registers

OFFSETACRONYMREGISTER NAME
0x000 SHA_ODIGEST_A SHA Outer Digest A
0x004 SHA_ODIGEST_B SHA Outer Digest B
0x008 SHA_ODIGEST_C SHA Outer Digest C
0x00C SHA_ODIGEST_D SHA Outer Digest D
0x010 SHA_ODIGEST_E SHA Outer Digest E
0x014 SHA_ODIGEST_F SHA Outer Digest F
0x018 SHA_ODIGEST_G SHA Outer Digest G
0x01C SHA_ODIGEST_H SHA Outer Digest H
0x020 SHA_IDIGEST_A SHA Inner Digest A
0x024 SHA_IDIGEST_B SHA Inner Digest B
0x028 SHA_IDIGEST_C SHA Inner Digest C
0x02C SHA_IDIGEST_D SHA Inner Digest D
0x030 SHA_IDIGEST_E SHA Inner Digest E
0x034 SHA_IDIGEST_F SHA Inner Digest F
0x038 SHA_IDIGEST_G SHA Inner Digest G
0x03C SHA_IDIGEST_H SHA Inner Digest H
0x40 SHA_DIGEST_COUNT SHA Digest Count
0x44 SHA_MODE SHA Mode
0x48 SHA_LENGTH SHA Length
0x080 SHA_DATA_0_IN SHA Data 0 Input
0x084 SHA_DATA_1_IN SHA Data 1 Input
0x088 SHA_DATA_2_IN SHA Data 2 Input
0x08C SHA_DATA_3_IN SHA Data 3 Input
0x090 SHA_DATA_4_IN SHA Data 4 Input
0x094 SHA_DATA_5_IN SHA Data 5 Input
0x098 SHA_DATA_6_IN SHA Data 6 Input
0x09C SHA_DATA_7_IN SHA Data 7 Input
0x0A0 SHA_DATA_8_IN SHA Data 8 Input
0x0A4 SHA_DATA_9_IN SHA Data 9 Input
0x0A8 SHA_DATA_10_IN SHA Data 10 Input
0x0AC SHA_DATA_11_IN SHA Data 11 Input
0x0B0 SHA_DATA_12_IN SHA Data 12 Input
0x0B4 SHA_DATA_13_IN SHA Data 13 Input
0x0B8 SHA_DATA_14_IN SHA Data 14 Input
0x0BC SHA_DATA_15_IN SHA Data 15 Input
0x100 SHA_REVISION SHA Revision
0x110 SHA_SYSCONFIG SHA System Configuration
0x114 SHA_SYSSTATUS SHA System Status
0x118 SHA_IRQSTATUS SHA Interrupt Status
0x11C SHA_IRQENABLE SHA Interrupt Enable

Table 6-29 SHA/MD5 µDMA Registers

OFFSETACRONYMREGISTER NAME
0x10 SHA_DMAIM SHA DMA Interrupt Mask
0x14 SHA_DMARIS SHA DMA Raw Interrupt Status
0x18 SHA_DMAMIS SHA DMA Masked Interrupt Status
0x1C SHA_DMAIC SHA DMA Interrupt Clear

Table 6-30 System Control Memory Registers

OFFSETACRONYMREGISTER NAME
0xD4 RVP Reset Vector Pointer
0x1D0 BOOTCFG Boot Configuration
0x1E0 to 0x1EC USER_REG_0 to USER_REG_3 User Register 0 to User Register 3
0x200 to 0x23C FMPRE_0 to FMPRE_15 Flash Memory Protection Read Enable 0 to Flash Memory Protection Read Enable 15
0x400 to 0x43C FMPPE_0 to FMPPE_15 Flash Memory Protection Program Enable 0 to Flash Memory Protection Program Enable 15

Table 6-31 System Exception Registers

OFFSETACRONYMREGISTER NAME
0x0 SYSEXCRIS System Exception Raw Interrupt Status
0x4 SYSEXCIM System Exception Interrupt Mask
0x8 SYSEXCMIS System Exception Masked Interrupt Status
0xC SYSEXCIC System Exception Interrupt Clear

Table 6-32 UART Registers

OFFSETACRONYMREGISTER NAME
0x0 UARTDR UART Data
0x4 UARTRSR/UARTECR UART Receive Status/Error Clear
0x18 UARTFR UART Flag
0x20 UARTILPR UART IrDA Low-Power Register
0x24 UARTIBRD UART Integer Baud-Rate Divisor
0x28 UARTFBRD UART Fractional Baud-Rate Divisor
0x2C UARTLCRH UART Line Control
0x30 UARTCTL UART Control
0x34 UARTIFLS UART Interrupt FIFO Level Select
0x38 UARTIM UART Interrupt Mask
0x3C UARTRIS UART Raw Interrupt Status
0x40 UARTMIS UART Masked Interrupt Status
0x44 UARTICR UART Interrupt Clear
0x48 UARTDMACTL UART DMA Control
0xA4 UART9BITADDR UART 9-Bit Self Address
0xA8 UART9BITAMASK UART 9-Bit Self Address Mask
0xFC0 UARTPP UART Peripheral Properties
0xFC8 UARTCC UART Clock Configuration
0xFD0 UARTPeriphID4 UART Peripheral Identification 4
0xFD4 UARTPeriphID5 UART Peripheral Identification 5
0xFD8 UARTPeriphID6 UART Peripheral Identification 6
0xFDC UARTPeriphID7 UART Peripheral Identification 7
0xFE0 UARTPeriphID0 UART Peripheral Identification 0
0xFE4 UARTPeriphID1 UART Peripheral Identification 1
0xFE8 UARTPeriphID2 UART Peripheral Identification 2
0xFEC UARTPeriphID3 UART Peripheral Identification 3
0xFF0 UARTPCellID0 UART PrimeCell Identification 0
0xFF4 UARTPCellID1 UART PrimeCell Identification 1
0xFF8 UARTPCellID2 UART PrimeCell Identification 2
0xFFC UARTPCellID3 UART PrimeCell Identification 3

Table 6-33 USB Registers

OFFSETACRONYMREGISTER NAME
0x0 USBFADDR USB Device Functional Address
0x1 USBPOWER USB Power
0x2 USBTXIS USB Transmit Interrupt Status
0x4 USBRXIS USB Receive Interrupt Status
0x6 USBTXIE USB Transmit Interrupt Enable
0x8 USBRXIE USB Receive Interrupt Enable
0xA USBIS USB General Interrupt Status
0xB USBIE USB Interrupt Enable
0xC USBFRAME USB Frame Value
0xE USBEPIDX USB Endpoint Index
0xF USBTEST USB Test Mode
0x20 USBFIFO0 USB FIFO Endpoint 0
0x24 USBFIFO1 USB FIFO Endpoint 1
0x28 USBFIFO2 USB FIFO Endpoint 2
0x2C USBFIFO3 USB FIFO Endpoint 3
0x30 USBFIFO4 USB FIFO Endpoint 4
0x34 USBFIFO5 USB FIFO Endpoint 5
0x38 USBFIFO6 USB FIFO Endpoint 6
0x3C USBFIFO7 USB FIFO Endpoint 7
0x60 USBDEVCTL USB Device Control
0x61 USBCCONF USB Common Configuration
0x62 USBTXFIFOSZ USB Transmit Dynamic FIFO Sizing
0x63 USBRXFIFOSZ USB Receive Dynamic FIFO Sizing
0x64 USBTXFIFOADD USB Transmit FIFO Start Address
0x66 USBRXFIFOADD USB Receive FIFO Start Address
0x70 ULPIVBUSCTL USB ULPI VBUS Control
0x74 ULPIREGDATA USB ULPI Register Data
0x75 ULPIREGADDR USB ULPI Register Address
0x76 ULPIREGCTL USB ULPI Register Control
0x78 USBEPINFO USB Endpoint Information
0x79 USBRAMINFO USB RAM Information
0x7A USBCONTIM USB Connect Timing
0x7B USBVPLEN USB OTG VBUS Pulse Timing
0x7C USBHSEOF USB High-Speed Last Transaction to End of Frame Timing
0x7D USBFSEOF USB Full-Speed Last Transaction to End of Frame Timing
0x7E USBLSEOF USB Low-Speed Last Transaction to End of Frame Timing
0x80 USBTXFUNCADDR0 USB Transmit Functional Address Endpoint 0
0x82 USBTXHUBADDR0 USB Transmit Hub Address Endpoint 0
0x83 USBTXHUBPORT0 USB Transmit Hub Port Endpoint 0
0x88 USBTXFUNCADDR1 USB Transmit Functional Address Endpoint 1
0x8A USBTXHUBADDR1 USB Transmit Hub Address Endpoint 1
0x8B USBTXHUBPORT1 USB Transmit Hub Port Endpoint 1
0x8C USBRXFUNCADDR1 USB Receive Functional Address Endpoint 1
0x8E USBRXHUBADDR1 USB Receive Hub Address Endpoint 1
0x8F USBRXHUBPORT1 USB Receive Hub Port Endpoint 1
0x90 USBTXFUNCADDR2 USB Transmit Functional Address Endpoint 2
0x92 USBTXHUBADDR2 USB Transmit Hub Address Endpoint 2
0x93 USBTXHUBPORT2 USB Transmit Hub Port Endpoint 2
0x94 USBRXFUNCADDR2 USB Receive Functional Address Endpoint 2
0x96 USBRXHUBADDR2 USB Receive Hub Address Endpoint 2
0x97 USBRXHUBPORT2 USB Receive Hub Port Endpoint 2
0x98 USBTXFUNCADDR3 USB Transmit Functional Address Endpoint 3
0x9A USBTXHUBADDR3 USB Transmit Hub Address Endpoint 3
0x9B USBTXHUBPORT3 USB Transmit Hub Port Endpoint 3
0x9C USBRXFUNCADDR3 USB Receive Functional Address Endpoint 3
0x9E USBRXHUBADDR3 USB Receive Hub Address Endpoint 3
0x9F USBRXHUBPORT3 USB Receive Hub Port Endpoint 3
0xA0 USBTXFUNCADDR4 USB Transmit Functional Address Endpoint 4
0xA2 USBTXHUBADDR4 USB Transmit Hub Address Endpoint 4
0xA3 USBTXHUBPORT4 USB Transmit Hub Port Endpoint 4
0xA4 USBRXFUNCADDR4 USB Receive Functional Address Endpoint 4
0xA6 USBRXHUBADDR4 USB Receive Hub Address Endpoint 4
0xA7 USBRXHUBPORT4 USB Receive Hub Port Endpoint 4
0xA8 USBTXFUNCADDR5 USB Transmit Functional Address Endpoint 5
0xAA USBTXHUBADDR5 USB Transmit Hub Address Endpoint 5
0xAB USBTXHUBPORT5 USB Transmit Hub Port Endpoint 5
0xAC USBRXFUNCADDR5 USB Receive Functional Address Endpoint 5
0xAE USBRXHUBADDR5 USB Receive Hub Address Endpoint 5
0xAF USBRXHUBPORT5 USB Receive Hub Port Endpoint 5
0xB0 USBTXFUNCADDR6 USB Transmit Functional Address Endpoint 6
0xB2 USBTXHUBADDR6 USB Transmit Hub Address Endpoint 6
0xB3 USBTXHUBPORT6 USB Transmit Hub Port Endpoint 6
0xB4 USBRXFUNCADDR6 USB Receive Functional Address Endpoint 6
0xB6 USBRXHUBADDR6 USB Receive Hub Address Endpoint 6
0xB7 USBRXHUBPORT6 USB Receive Hub Port Endpoint 6
0xB8 USBTXFUNCADDR7 USB Transmit Functional Address Endpoint 7
0xBA USBTXHUBADDR7 USB Transmit Hub Address Endpoint 7
0xBB USBTXHUBPORT7 USB Transmit Hub Port Endpoint 7
0xBC USBRXFUNCADDR7 USB Receive Functional Address Endpoint 7
0xBE USBRXHUBADDR7 USB Receive Hub Address Endpoint 7
0xBF USBRXHUBPORT7 USB Receive Hub Port Endpoint 7
0x102 USBCSRL0 USB Control and Status Endpoint 0 Low
0x103 USBCSRH0 USB Control and Status Endpoint 0 High
0x108 USBCOUNT0 USB Receive Byte Count Endpoint 0
0x10A USBTYPE0 USB Type Endpoint 0
0x10B USBNAKLMT USB NAK Limit
0x110 USBTXMAXP1 USB Maximum Transmit Data Endpoint 1
0x112 USBTXCSRL1 USB Transmit Control and Status Endpoint 1 Low
0x113 USBTXCSRH1 USB Transmit Control and Status Endpoint 1 High
0x114 USBRXMAXP1 USB Maximum Receive Data Endpoint 1
0x116 USBRXCSRL1 USB Receive Control and Status Endpoint 1 Low
0x117 USBRXCSRH1 USB Receive Control and Status Endpoint 1 High
0x118 USBRXCOUNT1 USB Receive Byte Count Endpoint 1
0x11A USBTXTYPE1 USB Host Transmit Configure Type Endpoint 1
0x11B USBTXINTERVAL1 USB Host Transmit Interval Endpoint 1
0x11C USBRXTYPE1 USB Host Configure Receive Type Endpoint 1
0x11D USBRXINTERVAL1 USB Host Receive Polling Interval Endpoint 1
0x120 USBTXMAXP2 USB Maximum Transmit Data Endpoint 2
0x122 USBTXCSRL2 USB Transmit Control and Status Endpoint 2 Low
0x123 USBTXCSRH2 USB Transmit Control and Status Endpoint 2 High
0x124 USBRXMAXP2 USB Maximum Receive Data Endpoint 2
0x126 USBRXCSRL2 USB Receive Control and Status Endpoint 2 Low
0x127 USBRXCSRH2 USB Receive Control and Status Endpoint 2 High
0x128 USBRXCOUNT2 USB Receive Byte Count Endpoint 2
0x12A USBTXTYPE2 USB Host Transmit Configure Type Endpoint 2
0x12B USBTXINTERVAL2 USB Host Transmit Interval Endpoint 2
0x12C USBRXTYPE2 USB Host Configure Receive Type Endpoint 2
0x12D USBRXINTERVAL2 USB Host Receive Polling Interval Endpoint 2
0x130 USBTXMAXP3 USB Maximum Transmit Data Endpoint 3
0x132 USBTXCSRL3 USB Transmit Control and Status Endpoint 3 Low
0x133 USBTXCSRH3 USB Transmit Control and Status Endpoint 3 High
0x134 USBRXMAXP3 USB Maximum Receive Data Endpoint 3
0x136 USBRXCSRL3 USB Receive Control and Status Endpoint 3 Low
0x137 USBRXCSRH3 USB Receive Control and Status Endpoint 3 High
0x138 USBRXCOUNT3 USB Receive Byte Count Endpoint 3
0x13A USBTXTYPE3 USB Host Transmit Configure Type Endpoint 3
0x13B USBTXINTERVAL3 USB Host Transmit Interval Endpoint 3
0x13C USBRXTYPE3 USB Host Configure Receive Type Endpoint 3
0x13D USBRXINTERVAL3 USB Host Receive Polling Interval Endpoint 3
0x140 USBTXMAXP4 USB Maximum Transmit Data Endpoint 4
0x142 USBTXCSRL4 USB Transmit Control and Status Endpoint 4 Low
0x143 USBTXCSRH4 USB Transmit Control and Status Endpoint 4 High
0x144 USBRXMAXP4 USB Maximum Receive Data Endpoint 4
0x146 USBRXCSRL4 USB Receive Control and Status Endpoint 4 Low
0x147 USBRXCSRH4 USB Receive Control and Status Endpoint 4 High
0x148 USBRXCOUNT4 USB Receive Byte Count Endpoint 4
0x14A USBTXTYPE4 USB Host Transmit Configure Type Endpoint 4
0x14B USBTXINTERVAL4 USB Host Transmit Interval Endpoint 4
0x14C USBRXTYPE4 USB Host Configure Receive Type Endpoint 4
0x14D USBRXINTERVAL4 USB Host Receive Polling Interval Endpoint 4
0x150 USBTXMAXP5 USB Maximum Transmit Data Endpoint 5
0x152 USBTXCSRL5 USB Transmit Control and Status Endpoint 5 Low
0x153 USBTXCSRH5 USB Transmit Control and Status Endpoint 5 High
0x154 USBRXMAXP5 USB Maximum Receive Data Endpoint 5
0x156 USBRXCSRL5 USB Receive Control and Status Endpoint 5 Low
0x157 USBRXCSRH5 USB Receive Control and Status Endpoint 5 High
0x158 USBRXCOUNT5 USB Receive Byte Count Endpoint 5
0x15A USBTXTYPE5 USB Host Transmit Configure Type Endpoint 5
0x15B USBTXINTERVAL5 USB Host Transmit Interval Endpoint 5
0x15C USBRXTYPE5 USB Host Configure Receive Type Endpoint 5
0x15D USBRXINTERVAL5 USB Host Receive Polling Interval Endpoint 5
0x160 USBTXMAXP6 USB Maximum Transmit Data Endpoint 6
0x162 USBTXCSRL6 USB Transmit Control and Status Endpoint 6 Low
0x163 USBTXCSRH6 USB Transmit Control and Status Endpoint 6 High
0x164 USBRXMAXP6 USB Maximum Receive Data Endpoint 6
0x166 USBRXCSRL6 USB Receive Control and Status Endpoint 6 Low
0x167 USBRXCSRH6 USB Receive Control and Status Endpoint 6 High
0x168 USBRXCOUNT6 USB Receive Byte Count Endpoint 6
0x16A USBTXTYPE6 USB Host Transmit Configure Type Endpoint 6
0x16B USBTXINTERVAL6 USB Host Transmit Interval Endpoint 6
0x16C USBRXTYPE6 USB Host Configure Receive Type Endpoint 6
0x16D USBRXINTERVAL6 USB Host Receive Polling Interval Endpoint 6
0x170 USBTXMAXP7 USB Maximum Transmit Data Endpoint 7
0x172 USBTXCSRL7 USB Transmit Control and Status Endpoint 7 Low
0x173 USBTXCSRH7 USB Transmit Control and Status Endpoint 7 High
0x174 USBRXMAXP7 USB Maximum Receive Data Endpoint 7
0x176 USBRXCSRL7 USB Receive Control and Status Endpoint 7 Low
0x177 USBRXCSRH7 USB Receive Control and Status Endpoint 7 High
0x178 USBRXCOUNT7 USB Receive Byte Count Endpoint 7
0x17A USBTXTYPE7 USB Host Transmit Configure Type Endpoint 7
0x17B USBTXINTERVAL7 USB Host Transmit Interval Endpoint 7
0x17C USBRXTYPE7 USB Host Configure Receive Type Endpoint 7
0x17D USBRXINTERVAL7 USB Host Receive Polling Interval Endpoint 7
0x200 USBDMAINTR USB DMA Interrupt
0x204 USBDMACTL0 USB DMA Control 0
0x208 USBDMAADDR0 USB DMA Address 0
0x20C USBDMACOUNT0 USB DMA Count 0
0x214 USBDMACTL1 USB DMA Control 1
0x218 USBDMAADDR1 USB DMA Address 1
0x21C USBDMACOUNT1 USB DMA Count 1
0x224 USBDMACTL2 USB DMA Control 2
0x228 USBDMAADDR2 USB DMA Address 2
0x22C USBDMACOUNT2 USB DMA Count 2
0x234 USBDMACTL3 USB DMA Control 3
0x238 USBDMAADDR3 USB DMA Address 3
0x23C USBDMACOUNT3 USB DMA Count 3
0x244 USBDMACTL4 USB DMA Control 4
0x248 USBDMAADDR4 USB DMA Address 4
0x24C USBDMACOUNT4 USB DMA Count 4
0x254 USBDMACTL5 USB DMA Control 5
0x258 USBDMAADDR5 USB DMA Address 5
0x25C USBDMACOUNT5 USB DMA Count 5
0x264 USBDMACTL6 USB DMA Control 6
0x268 USBDMAADDR6 USB DMA Address 6
0x26C USBDMACOUNT6 USB DMA Count 6
0x274 USBDMACTL7 USB DMA Control 7
0x278 USBDMAADDR7 USB DMA Address 7
0x27C USBDMACOUNT7 USB DMA Count 7
0x304 USBRQPKTCOUNT1 USB Request Packet Count in Block Transfer Endpoint 1
0x308 USBRQPKTCOUNT2 USB Request Packet Count in Block Transfer Endpoint 2
0x30C USBRQPKTCOUNT3 USB Request Packet Count in Block Transfer Endpoint 3
0x310 USBRQPKTCOUNT4 USB Request Packet Count in Block Transfer Endpoint 4
0x314 USBRQPKTCOUNT5 USB Request Packet Count in Block Transfer Endpoint 5
0x318 USBRQPKTCOUNT6 USB Request Packet Count in Block Transfer Endpoint 6
0x31C USBRQPKTCOUNT7 USB Request Packet Count in Block Transfer Endpoint 7
0x340 USBRXDPKTBUFDIS USB Receive Double Packet Buffer Disable
0x342 USBTXDPKTBUFDIS USB Transmit Double Packet Buffer Disable
0x344 USBCTO USB Chirp Time-out
0x346 USBHHSRTN USB High Speed to UTM Operating Delay
0x348 USBHSBT USB High Speed Time-out Adder
0x360 USBLPMATTR USB LPM Attributes
0x362 USBLPMCNTRL USB LPM Control
0x363 USBLPMIM USB LPM Interrupt Mask
0x364 USBLPMRIS USB LPM Raw Interrupt Status
0x365 USBLPMFADDR USB LPM Function Address
0x400 USBEPC USB External Power Control
0x404 USBEPCRIS USB External Power Control Raw Interrupt Status
0x408 USBEPCIM USB External Power Control Interrupt Mask
0x40C USBEPCISC USB External Power Control Interrupt Status and Clear
0x410 USBDRRIS USB Device RESUME Raw Interrupt Status
0x414 USBDRIM USB Device RESUME Interrupt Mask
0x418 USBDRISC USB Device RESUME Interrupt Status and Clear
0x41C USBGPCS USB General-Purpose Control and Status
0x430 USBVDC USB VBUS Droop Control
0x434 USBVDCRIS USB VBUS Droop Control Raw Interrupt Status
0x438 USBVDCIM USB VBUS Droop Control Interrupt Mask
0x43C USBVDCISC USB VBUS Droop Control Interrupt Status and Clear
0xFC0 USBPP USB Peripheral Properties
0xFC4 USBPC USB Peripheral Configuration
0xFC8 USBCC USB Clock Configuration

Table 6-34 WDT Registers

OFFSETACRONYMREGISTER NAME
0x0 WDTLOAD Watchdog Load
0x4 WDTVALUE Watchdog Value
0x8 WDTCTL Watchdog Control
0xC WDTICR Watchdog Interrupt Clear
0x10 WDTRIS Watchdog Raw Interrupt Status
0x14 WDTMIS Watchdog Masked Interrupt Status
0x418 WDTTEST Watchdog Test
0xC00 WDTLOCK Watchdog Lock
0xFD0 WDTPeriphID4 Watchdog Peripheral Identification 4
0xFD4 WDTPeriphID5 Watchdog Peripheral Identification 5
0xFD8 WDTPeriphID6 Watchdog Peripheral Identification 6
0xFDC WDTPeriphID7 Watchdog Peripheral Identification 7
0xFE0 WDTPeriphID0 Watchdog Peripheral Identification 0
0xFE4 WDTPeriphID1 Watchdog Peripheral Identification 1
0xFE8 WDTPeriphID2 Watchdog Peripheral Identification 2
0xFEC WDTPeriphID3 Watchdog Peripheral Identification 3
0xFF0 WDTPCellID0 Watchdog PrimeCell Identification 0
0xFF4 WDTPCellID1 Watchdog PrimeCell Identification 1
0xFF8 WDTPCellID2 Watchdog PrimeCell Identification 2
0xFFC WDTPCellID3 Watchdog PrimeCell Identification 3