SLASEL0B October 2019 – June 2020 DAC11001A , DAC81001 , DAC91001
PRODUCTION DATA.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Read/Write | Address | 00h | |||||||||||||
R/W | W | W | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
00h | RCLTMP | 0h | SRST | SCLR | 0h | 0h | |||||||||
W | R/W | W | R/W | R/W | W | W |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | Read/Write | R/W | N/A | Read when set to 1 or write when set to 0 |
30:24 | Address | W | N/A | 04h |
23:9 | 0000h | W | N/A | Unused |
8 | RCLTMP | R/W | 0h | Trigger temperature recalibration DAC Codes
0 : No temperature recalibration (default) 1 : DAC codes recalibrated, ALARM pin is pulled low (if ENALMP = 1) and ALM bit (Address 05) is set 1 upon calibration completion. Subsequent DAC codes will use latest calibrated coefficients. |
7 | 0h | W | N/A | NA |
6 | SRST | R/W | 0h | Software reset
0 : No software reset (default) 1 : Software reset initiated, device in default state |
5 | SCLR | R/W | 0h | Software clear
0 : No software clear (default) 1 : Software clear initiated, DAC registers in clear mode, DAC code set by clear select register (address 03h). DAC output clears on 32nd SCLK falling (DSDO = 1) or SYNC rising edge (DSDO = 0) |
4 | 0h | W | N/A | N/A |
3:0 | 0h | W | N/A | N/A |