Table 6-1 Interrupts

6.5.6.1 Ethernet MAC and PHY

The Ethernet controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface with the following features:

• Conforms to the IEEE 802.3 specification
  • 10BASE-T and 100BASE-TX IEEE-802.3 compliant
  • Supports 10- and 100-Mbps data transmission rates
  • Supports full-duplex and half-duplex (CSMA/CD) operation
  • Supports flow control and back pressure
  • Full-featured and enhanced auto-negotiation
  • Supports IEEE 802.1Q VLAN tag detection
• Conforms to IEEE 1588-2002 timestamp PTP protocol and the IEEE 1588-2008 advanced timestamp specification
  • Transmit and receive frame timestamping
  • Precision time protocol
  • Flexible pulse per second output
  • Supports coarse and fine correction methods
• Multiple addressing modes
  • Four MAC address filters
  • Programmable 64-bit hash filter for multicast address filtering
  • Promiscuous mode support
• Processor offloading
  • Programmable insertion (TX) or deletion (RX) of preamble and start-of-frame data
  • Programmable generation (TX) or deletion (RX) of CRC and pad data
  • IP header and hardware checksum checking (IPv4, IPv6, TCP, UDP, ICMP)
• Highly configurable
  • LED activity selection
  • Supports network statistics with RMON and MIB counters
  • Supports magic packet and wake-up frames
• Efficient transfers using integrated µDMA
  • Dual-buffer (ring) or linked-list (chained) descriptors
  • Round-robin or fixed priority arbitration between TX and RX
  • Descriptors support transfer blocks size up to 8KB
  • Programmable interrupts for flexible system implementation
• Physical media manipulation
  • MDI/MDI-X cross-over support
  • Register-programmable transmit amplitude
  • Automatic polarity correction and 10BASE-T signal reception

6.5.6.2 Controller Area Network (CAN)

CAN is a multicast shared serial-bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy environments and can use a differential balanced line like RS-485 or twisted-pair wire. Originally created for automotive purposes, it is now used in many embedded control applications (for example, industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters. Decreased bit rates allow longer network distances (for example, 125 kbps at 500 m).

A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis of the identifier received whether it should process the message. The identifier also determines the priority that the message enjoys in competition for bus access. Each CAN message can transmit from 0 to 8 bytes of user information.

Each of the two CAN units includes the following features:

• CAN protocol version 2.0 part A/B
• Bit rates up to 1 Mbps
• 32 message objects with individual identifier masks
• Maskable interrupt
• Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
• Programmable loopback mode for self-test operation
• Programmable FIFO mode enables storage of multiple message objects
• Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals

6.5.6.3 Universal Serial Bus (USB)

USB is a serial bus standard designed to allow connection and disconnection of peripherals using a standardized interface without rebooting the system.

One USB controller supports high-speed and full-speed multiple-point communications and complies with the USB 2.0 standard for high-speed function. The USB controller can have three configurations: USB device, USB host, and USB OTG (negotiated on-the-go as host or device when connected to other USB-enabled systems). Support for full-speed communication is provided by using the integrated USB PHY or optionally, a high-speed ULPI can communicate to an external PHY.

The USB module has the following features:

• Complies with USB-IF (Implementer's Forum) certification standards
• USB 2.0 high-speed (480 Mbps) operation with the integrated ULPI communicating with an external PHY
• Link power-management support that uses link-state awareness to reduce power usage
• Four transfer types: control, interrupt, bulk, and isochronous
• 16 endpoints
  • 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint
  • 7 configurable IN endpoints and 7 configurable OUT endpoints
• 4KB of dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte isochronous packet size
• VBUS droop detection and interrupt
• Integrated USB DMA with bus master capability
  • Up to eight RX endpoint channels and up to eight TX endpoint channels are available.
  • Each channel can be separately programmed to operate in different modes.
  • Incremental burst transfers of 4, 8, 16, or unspecified length supported

6.5.6.4 Universal Asynchronous Receiver/Transmitter (UART)

A UART is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately.

Eight fully programmable 16C550-type UARTs are integrated. Although the functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART can generate individually masked interrupts from the RX, TX, modem flow control, modem status, and error conditions. The module generates one combined interrupt when any of the interrupts are asserted and are unmasked.

The UARTs have the following features:

• Programmable baud-rate generator allowing speeds up to 7.5 Mbps for regular speed (divide by 16) and 15 Mbps for high speed (divide by 8)
• Separate 16×8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
• Programmable FIFO length, including a 1-byte-deep operation providing conventional double-buffered interface
• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
• Standard asynchronous communication bits for start, stop, and parity
• Line-break generation and detection
• Fully programmable serial interface characteristics
  • 5, 6, 7, or 8 data bits
  • Even, odd, stick, or no-parity bit generation/detection
  • 1 or 2 stop bit generation
• IrDA serial-IR (SIR) encoder and decoder providing
  • Programmable use of IrDA Serial Infrared (SIR) or UART I/O
  • Support of IrDA SIR encoder and decoder functions for data rates up to 115.2 kbps half-duplex
  • Support of normal 3/16 and low-power (1.41 to 2.23 µs) bit durations
  • Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration
• Support for communication with ISO 7816 smart cards
• Modem functionality available on the following UARTs:
  • UART0 (modem flow control and modem status)
  • UART1 (modem flow control and modem status)
  • UART2 (modem flow control)
  • UART3 (modem flow control)
  • UART4 (modem flow control)
• EIA-485 9-bit support
• Standard FIFO-level and end-of-transmission interrupts
• Efficient transfers using µDMA
  • Separate channels for transmit and receive
  • Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level
  • Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level
• The Global Alternate Clock (ALTCLK) resource or System Clock (SYSCLK) can be used to generate the baud clock

6.5.6.5 Inter-Integrated Circuit (I²C)

The I²C bus provides bidirectional data transfer through a 2-wire design (a serial data line SDA and a serial clock line SCL). The I²C bus interfaces to external I²C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I²C bus can also be used for system testing and diagnostic purposes in product development and manufacture.

Each device on the I²C bus can be designated as either a master or a slave. The I2C module supports both sending and receiving data as either a master or a slave and can operate simultaneously as both a master and a slave. Both the I²C master and slave can generate interrupts.

The I2C modules include the following features:

• Devices on the I²C bus can be designated as either a master or a slave
  • Supports both transmitting and receiving data as either a master or a slave
  • Supports simultaneous master and slave operation
• Four I²C modes
  • Master transmit
  • Master receive
  • Slave transmit
  • Slave receive
• Two 8-entry FIFOs for receive and transmit data
  • FIFOs can be independently assigned to master or slave
• Four transmission speeds:
  • Standard (100 kbps)
  • Fast-mode (400 kbps)
  • Fast-mode plus (1 Mbps)
  • High-speed mode (3.33 Mbps)
• Glitch suppression
• SMBus support through software
  • Clock low time-out interrupt
  • Dual slave address capability
  • Quick command capability
• Master and slave interrupt generation
  • Master generates interrupts when a transmit or receive operation completes (or aborts due to an error)
  • Slave generates interrupts when data has been transferred or requested by a master or when a START or STOP condition is detected
• Master with arbitration and clock synchronization, multiple-master support, and 7-bit addressing mode
• Efficient transfers using µDMA
  • Separate channels for transmit and receive
  • Ability to execute single data transfers or burst data transfers using the RX and TX FIFOs in the I²C

6.5.6.6 Quad Synchronous Serial Interface (QSSI)

QSSI is a bidirectional communications interface that converts data between parallel and serial. The QSSI module performs serial-to-parallel conversion on data received from a peripheral device and performs parallel-to-serial conversion on data transmitted to a peripheral device. The QSSI module can be configured as either a master or slave device. As a slave device, the QSSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs.

The QSSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the input clock of the QSSI module. Bit rates are generated based on the input clock, and the maximum bit rate is determined by the connected peripheral.

The four QSSI modules each support the following features:

• Four QSSI channels with advanced, bi-SSI, and quad-SSI functionality
• Programmable interface operation for Freescale SPI or TI synchronous serial interfaces in legacy mode. Support for Freescale interface in Bi- and Quad-SSI mode.
• Master or slave operation
• Programmable clock bit rate and prescaler
• Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
• Programmable data frame size from 4 to 16 bits
• Internal loopback test mode for diagnostic/debug testing
• Standard FIFO-based interrupts and end-of-transmission interrupt
• Efficient transfers using µDMA
  • Separate channels for transmit and receive
  • Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains four entries
  • Transmit single request asserted when there is space in the FIFO; burst request asserted when four or more entries are available to be written in the FIFO
  • Maskable µDMA interrupts for receive and transmit complete
• Global alternate clock (ALTCLK) resource or system clock (SYSCLK) can be used to generate baud clock.

6.5.7.1 Direct Memory Access (DMA)

The DMA controller is known as micro-DMA (µDMA). The µDMA controller provides a way to offload data transfer tasks from the Cortex-M4F processor, allowing for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The µDMA controller provides the following features:

• Arm PrimeCell 32-channel configurable µDMA controller
• Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes
  • Basic for simple transfer scenarios
  • Ping-pong for continuous data flow
  • Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from one request
• Highly flexible and configurable channel operation
  • Independently configured and operated channels
  • Dedicated channels for supported on-chip modules
  • Flexible channel assignments
  • One channel each for receive and transmit path for bidirectional modules
  • Dedicated channel for software-initiated transfers
  • Per-channel configurable priority scheme
  • Optional software-initiated requests for any channel
• Two levels of priority
• Design optimizations for improved bus access performance between µDMA controller and the processor core
  • µDMA controller access is subordinate to core access
  • RAM striping
  • Peripheral bus segmentation
• Data sizes of 8, 16, and 32 bits
• Transfer size is programmable in binary steps from 1 to 1024
• Source and destination address increment size of byte, halfword, word, or no increment
• Maskable peripheral requests
• Interrupt on transfer completion, with a separate interrupt per channel

Each DMA channel has up to nine possible assignments that are selected using the DMA Channel Map Select n (DMACHMAPn) registers with 4-bit assignment fields for each µDMA channel.

Table 6-2 lists the µDMA channel mapping. The Encoding column lists the encoding for the respective DMACHMAPn bit field. Encodings 0x9 to 0xF are reserved. The Type column indicates if a particular peripheral uses a single request (S), burst request (B), or either (SB).

6.5.7.2 System Control and Clocks

System control determines the overall operation of the device. It provides information about the device, controls power-saving features, controls the clocking of the device and individual peripherals, and handles reset detection and reporting.

• Device identification information: version, part number, SRAM size, flash memory size, and so on
• Power control
  • On-chip fixed low dropout (LDO) voltage regulator
  • Hibernation module manages the power-up and power-down 3.3-V sequencing and control for the core digital logic and analog circuits
  • Low-power options for MCU: sleep and deep-sleep modes with clock gating
  • Low-power options for on-chip modules: software controls shutdown of individual peripherals and memory
  • 3.3-V supply brownout detection and reporting through interrupt or reset
• Multiple clock sources for the system clock. The MCU is clocked by the system clock (SYSCLK) that is distributed to the processor and integrated peripherals after clock gating. The SYSCLK frequency is based on the frequency of the clock source and a divisor factor. A PLL is provided for the generation of system clock frequencies in excess of the reference clock provided. The reference clocks for the PLL are the PIOSC and the main crystal oscillator. The following clock sources are provided to the MCU:
  • 16-MHz precision oscillator (PIOSC)
  • Main oscillator (MOSC): A frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins.
  • Low-frequency internal oscillator (LFIOSC): On-chip resource used during power-saving modes.
  • Hibernate RTC oscillator (RTCOSC): A clock that can be configured to be the 32.768-kHz external oscillator source from the HIB module or the HIB low-frequency clock source (HIB LFIOSC), which is in the HIB module.
• Flexible reset sources
  • Power-on reset (POR)
  • Reset pin assertion
  • Brownout reset (BOR) detector alerts to system power drops
  • Software reset
  • Watchdog timer reset
  • Hibernation module event
  • MOSC failure
• 128-bit unique identifier for individual device identification

6.5.7.3 Programmable Timers

Programmable timers can be used to count or time external events that drive the Timer input pins. Each 16- or 32-bit General-Purpose Timer Module (GPTM) block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters. These two timers/counters can also be configured to operate as one 32-bit timer or one 32-bit RTC. Timers can also be used to trigger analog-to-digital conversions and DMA transfers.

The GPTM contains eight 16- or 32-bit GPTM blocks with the following functional options:

• Operating modes
  • 16- or 32-bit programmable one-shot timer
  • 16- or 32-bit programmable periodic timer
  • 16-bit general-purpose timer with an 8-bit prescaler
  • 32-bit RTC when using an external 32.768-kHz clock as the input
  • 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
  • 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM signal
• Count up or down
• Sixteen 16- or 32-bit capture/compare PWM (CCP) pins
• Daisy-chaining of timer modules lets one timer initiate multiple timing events
• Timer synchronization lets selected timers start counting on the same clock cycle
• ADC event trigger
• User-enabled stalling when the MCU asserts the CPU halt flag during debug (excluding RTC mode)
• Can determine the elapsed time between the assertion of the timer interrupt and entry into the ISR
• Efficient transfers using µDMA
  • Dedicated channel for each timer
  • Burst request generated on timer interrupt

6.5.7.4 Capture Compare PWM (CCP) Pins

CCP pins can be used by the General-Purpose Timer module to time or count external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM output on the CCP pin.

The 16/32-bit CCP pins can be programmed to operate in the following modes:

• Capture: The GP timer is incremented or decremented by programmed events on the CCP input. The GP timer captures and stores the current timer value when a programmed event occurs.
• Compare: The GP timer is incremented or decremented by programmed events on the CCP input. The GP timer compares the current value with a stored value and generates an interrupt when a match occurs.
• PWM: The GP timer is incremented or decremented by the system clock. A PWM signal is generated based on a match between the counter value and a value stored in a match register and is output on the CCP pin.

6.5.7.5 Hibernation (HIB) Module

The HIB module provides logic to switch power off to the main processor and peripherals and to wake on external or time-based events. The HIB module includes power-sequencing logic and has the following features:

• 32-bit RTC with 1/32768-second resolution and a 15-bit subseconds counter
  • 32-bit RTC seconds match register and a 15-bit subseconds match for timed wakeup and interrupt generation with 1/32768-second resolution
  • RTC predivider trim for making fine adjustments to the clock rate
• Hardware calendar function
  • Year, month, day, day of week, hours, minutes, and seconds
  • Four-year leap compensation
  • 24-hour or AM and PM configuration
• Two mechanisms for power control
  • System power control using a discrete external regulator
  • On-chip power control using internal switches under register control
• V_DD supplies power when valid, even if V_BAT > V_DD
• Dedicated pin for wake using an external signal
• Can configure the external reset (RST) pin or up to four GPIO port pins as wake sources, with programmable wake level
• Tamper functionality
  • Support for four tamper inputs
  • Configurable level, weak pullup, and glitch filter
  • Configurable tamper event response
  • Logging of up to four tamper events
  • Optional BBRAM erase on tamper detection
  • Tamper detection and wake-from-hibernate capability
  • Hibernation clock input failure detect with a switch to the internal oscillator on detection
• RTC operational and hibernation memory valid as long as V_DD or V_BAT is valid
• Low-battery detection, signaling, and interrupt generation, with optional wake on low battery
• GPIO pin state can be retained during hibernation
• Clock source from an internal low-frequency oscillator (HIB LFIOSC) or a 32.768-kHz external crystal or oscillator
• Sixteen 32-bit words of battery-backed memory to save state during hibernation
• Programmable interrupts for:
  • RTC match
  • External wake
  • Low battery

6.5.7.6 Watchdog Timers

A watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The watchdog timer can generate an interrupt, a nonmaskable interrupt, or a reset when a time-out value is reached. In addition, the watchdog timer is Arm FiRM-compliant and can be configured to generate an interrupt to the MCU on its first time-out, and to generate a reset signal on its second time-out. After the watchdog timer has been configured, the lock register can be written to prevent inadvertently altering the timer configuration.

Two watchdog timer modules are supported: Watchdog Timer 0 uses the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The watchdog timer module has the following features:

• 32-bit down counter with a programmable load register
• Separate watchdog clock with an enable
• Programmable interrupt generation logic with interrupt masking and optional NMI function
• Lock register protection from runaway software
• Reset generation logic with an enable/disable
• User-enabled stalling when the MCU asserts the CPU Halt flag during debug

6.5.7.7 Programmable GPIOs

General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The GPIO module is composed of 15 physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the Arm Foundation IP for Real-Time MCUs specification) and supports 0 to 90 programmable I/O pins. The number of GPIOs available depends on the peripherals being used.

• Up to 90 GPIOs, depending on configuration
• Highly flexible pin multiplexing allows use as GPIO or one of several peripheral functions
• 3.3-V tolerant in input configuration
• Advanced high-performance bus (AHB) accesses all ports:
  • Ports A to H, K to N, P, and Q
• Fast toggle capable of a change every clock cycle for ports on AHB
• Programmable control for GPIO interrupts
  • Interrupt generation masking
  • Edge-triggered on rising, falling, or both
  • Level-sensitive on high or low values
  • Per-pin interrupts available on port P and port Q
• Bit masking in both read and write operations through address lines
• Can be used to initiate an ADC sample sequence or a µDMA transfer
• Pin state can be retained during hibernation mode; pins on port P can be programmed to wake on level in hibernation mode
• Pins configured as digital inputs are Schmitt triggered
• Programmable control for GPIO pad configuration
  • Weak pullup or pulldown resistors
  • 2-, 4-, 6-, 8-, 10-, or 12-mA pad drive for digital communication; up to four pads can sink 18-mA for high-current applications
  • Slew rate control for 8-, 10-, and 12-mA pad drive
  • Open-drain enables
  • Digital-input enables

6.5.8.1 Pulse Width Modulation (PWM)

PWM is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control.

One PWM module is included, with four PWM generator blocks and a control block, for a total of eight PWM outputs. Each PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a dead-band generator, and an interrupt or ADC-trigger selector.

Each PWM generator block produces two PWM signals that can be either independent signals or a pair of complementary signals with dead-band delays inserted.

Each PWM generator has the following features:

• Four fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage to the motor being controlled
• One 16-bit counter
  • Runs in down or up/down mode
  • Output frequency controlled by a 16-bit load value
  • Synchronized load value updates
  • Produces output signals at zero and load value
• Two PWM comparators
  • Synchronized comparator value updates
  • Produces output signals on match
• PWM signal generator
  • Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals.
  • Produces two independent PWM signals
• Dead-band generator
  • Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge
  • Can be bypassed, leaving input PWM signals unmodified
• Can initiate an ADC sample sequence

The control block determines the polarity of the PWM signals and which signals are passed through to the pins. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. The PWM control block has the following options:

• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
• Synchronization of timer/comparator updates across the PWM generator blocks
• Extended PWM synchronization of timer/comparator updates across the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
• Extended PWM fault handling, with multiple fault signals, programmable polarities, and filtering
• PWM generators can be operated independently or synchronized with other generators

6.5.8.2 Quadrature Encoder With Index (QEI) Module

A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, the position, direction of rotation, and speed can be tracked. In addition, a third channel, or index signal, can be used to reset the position counter. The QEI module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel. The input frequency of the QEI inputs may be as high as 1/4 of the system frequency (for example, 30 MHz for a 120-MHz system).

One QEI module provides control of one motor with the following features:

• Position integrator that tracks the encoder position
• Programmable noise filter on the inputs
• Velocity capture using built-in timer
• The input frequency of the QEI inputs may be as high as 1/4 of the system frequency (for example, 12.5 MHz for a 50-MHz system)
• Interrupt generation on:
  • Index pulse
  • Velocity-timer expiration
  • Direction change
  • Quadrature error detection

6.5.9.1 ADC

An ADC is a peripheral that converts a continuous analog voltage to a discrete digital number. The ADC module features 12-bit conversion resolution and supports 20 input channels plus an internal temperature sensor. Four buffered sample sequencers allow rapid sampling of up to 20 analog input sources without controller intervention. Each sample sequencer provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequencer priority. Each ADC module has a digital comparator function that lets the conversion value be sent to a comparison unit that provides eight digital comparators.

Both ADC modules support the following features:

• 20 shared analog input channels
• 12-bit precision ADC
• Single-ended and differential-input configurations
• On-chip internal temperature sensor
• Maximum sample rate of two million samples/second
• Optional, programmable phase delay
• Sample and hold window programmability
• Four programmable sample conversion sequencers from one to eight entries long, with corresponding conversion result FIFOs
• Flexible trigger control
  • Controller (software)
  • Timers
  • Analog comparators
  • PWM
  • GPIO
• Hardware averaging of up to 64 samples
• Eight digital comparators
• Converter uses two external reference signals (VREFA+ and VREFA–) or VDDA and GNDA as the voltage reference
• Power and ground for the analog circuitry is separate from the digital power and ground
• Efficient transfers using µDMA
  • Dedicated channel for each sample sequencer
  • ADC module uses burst requests for DMA
• Global Alternate Clock (ALTCLK) resource or System Clock (SYSCLK) can be used to generate ADC clock.

6.5.9.2 Analog Comparators

An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. The independent integrated analog comparators can be configured to drive an output or generate an interrupt or ADC event.

The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge.

Each analog comparator supports the following functions:

• Compare external pin input to external pin input or to internal programmable voltage reference
• Compare a test voltage against any one of the following voltages:
  • An individual external reference voltage
  • A shared single external reference voltage
  • A shared internal reference voltage

Table 6-3 Memory Map

Table 6-4 AES Registers

Table 6-5 AES µDMA Registers

Table 6-6 ADC Registers

Table 6-7 CAN Registers

Table 6-8 Comparator Registers

Table 6-9 CRC Registers

Table 6-10 DES Registers

Table 6-11 DES µDMA Registers

Table 6-12 EEPROM Registers

Table 6-13 EPI Registers

Table 6-14 Ethernet MAC (EMAC) Registers

Table 6-15 Ethernet MII Management (EPHY) Registers (Accessed Through the EMACMIIADDR Register)

Table 6-16 Flash Registers

Table 6-17 GPIO Registers

Table 6-18 GPTM Registers

Table 6-19 HIB Registers

Table 6-20 I2C Registers

Table 6-21 µDMA Registers

Table 6-22 µDMA Channel Control Structure Registers

Table 6-23 PWM Registers

Table 6-24 QEI Registers

Table 6-25 QSSI Registers

Table 6-26 SHA/MD5 Registers

Table 6-27 SHA/MD5 µDMA Registers

Table 6-28 System Control Memory Registers

Table 6-29 System Exception Registers

Table 6-30 UART Registers

Table 6-31 USB Registers

Table 6-32 WDT Registers