SLASEQ4A October 2018 – December 2018 DAC43608 , DAC53608
PRODUCTION DATA.
The device stores the data written to the DAC Data registers in the DAC buffer registers. Transfer of data from the DAC buffer registers to the DAC active registers can be set to happen immediately (asynchronous mode) or initiated by an LDAC trigger (synchronous mode). Once the DAC active registers are updated, the DAC outputs change to their new values.
The update mode for each DAC channel is determined by the status of LDAC pin.
In asynchronous mode (LDAC = 0 before the DAC write command), a write to the DAC data register results in an immediate update of the DAC active register and DAC output at the end of I2CTM frame.
In synchronous mode (LDAC = 1 before the DAC write command), writing to the DAC data register does not automatically update the DAC output. Instead the update occurs only after an LDAC is pulled to 0. The synchronous update mode enables simultaneous update of all DAC outputs.