SLASER3A
July 2018 – November 2018
DAC61408
,
DAC71408
,
DAC81408
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Functional Block Diagram
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Digital-to-Analog Converters (DACs) Architecture
9.3.1.1
DAC Transfer Function
9.3.1.2
DAC Register Structure
9.3.1.2.1
DAC Register Synchronous and Asynchronous Updates
9.3.1.2.2
Broadcast DAC Register
9.3.1.2.3
Clear DAC Operation
9.3.2
Internal Reference
9.3.3
Device Reset Options
9.3.3.1
Power-on-Reset (POR)
9.3.3.2
Hardware Reset
9.3.3.3
Software Reset
9.3.4
Thermal Protection
9.3.4.1
Analog Temperature Sensor: TEMPOUT Pin
9.3.4.2
Thermal Shutdown
9.4
Device Functional Modes
9.4.1
Toggle Mode
9.4.2
Differential Mode
9.4.3
Power-Down Mode
9.5
Programming
9.5.1
Stand-Alone Operation
9.5.1.1
Streaming Mode Operation
9.5.2
Daisy-Chain Operation
9.5.3
Frame Error Checking
9.6
Register Maps
9.6.1
NOP Register (Offset = 00h) [reset = 0000h]
Table 9.
NOP Register Field Descriptions
9.6.2
DEVICEID Register (Offset = 01h) [reset = ----h]
Table 10.
DEVICEID Register Field Descriptions
9.6.3
STATUS Register (Offset = 02h) [reset = 0000h]
Table 11.
STATUS Register Field Descriptions
9.6.4
SPICONFIG Register (Offset = 03h) [reset = 0A24h]
Table 12.
SPICONFIG Register Field Descriptions
9.6.5
GENCONFIG Register (Offset = 04h) [reset = 7F00h]
Table 13.
GENCONFIG Register Field Descriptions
9.6.6
BRDCONFIG Register (Offset = 05h) [reset = FFFFh]
Table 14.
BRDCONFIG Register Field Descriptions
9.6.7
SYNCCONFIG Register (Offset = 06h) [reset = 0000h]
Table 15.
SYNCCONFIG Register Field Descriptions
9.6.8
TOGGCONFIG0 Register (Offset = 07h) [reset = 0000h]
Table 16.
TOGGCONFIG0 Register Field Descriptions
9.6.9
TOGGCONFIG1 Register (Offset = 08h) [reset = 0000h]
Table 17.
TOGGCONFIG1 Register Field Descriptions
9.6.10
DACPWDWN Register (Offset = 09h) [reset = FFFFh]
Table 18.
DACPWDWN Register Field Descriptions
9.6.11
DACRANGEn Register (Offset = 0Bh - 0Ch) [reset = 0000h]
Table 19.
DACRANGEn Register Field Descriptions
9.6.12
TRIGGER Register (Offset = 0Eh) [reset = 0000h]
Table 20.
TRIGGER Register Field Descriptions
9.6.13
BRDCAST Register (Offset = 0Fh) [reset = 0000h]
Table 21.
BRDCAST Register Field Descriptions
9.6.14
DACn Register (Offset = 14h - 1Bh) [reset = 0000h]
Table 22.
DACn Register Field Descriptions
9.6.15
OFFSETn Register (Offset = 21h - 22h) [reset = 0000h]
Table 23.
OFFSETn Register Field Descriptions
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure for Remote Ground Tracking
10.2.2.1
Generating 300mV Offset
10.2.2.2
Amplifier Selection
10.2.2.3
Passive Component Selection
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Documentation Support
13.2
Related Links
13.3
Receiving Notification of Documentation Updates
13.4
Community Resources
13.5
Trademarks
13.6
Electrostatic Discharge Caution
13.7
Glossary
14
Mechanical, Packaging, and Orderable Information
8
Parameter Measurement Information
Figure 45.
Serial Interface Write Timing Diagram
Figure 46.
Serial Interface Read Timing Diagram