SLASEW8A October 2020 – September 2023 DAC43701-Q1 , DAC53701-Q1
PRODUCTION DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
X | MARGIN_HIGH[9:0] / MARGIN_HIGH[7:0] – MSB Left aligned | X | |||||||||||||
X-0h | R/W-device-specific | X-00 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | X | X | 0h | Don't care |
11:2 | MARGIN_HIGH[9:0] / MARGIN_HIGH[7:0] – MSB Left aligned | R/W | Device-specific | Margin high code for DAC output. Data are in straight binary format and use the following format: DACx3701-Q1: {MARGIN_HIGH[[9:0]} DACx3701-Q1: {MARGIN_HIGH[[7:0], X, X} X = Don’t care bits The MARGIN_HIGH[7:0] bits store the oscillator frequency error for every device with 0.15%/LSB resolution in the NVM. An overwrite to this NVM field clears the error information permanently. See Section 7.4.2 for the error calculation. |
1:0 | X | X | 00 | Don't care |