SLASF03 December   2021 DAC11001B

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5 V
    7. 6.7  Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5 V
    8. 6.8  Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤ DVDD ≤ 5.5 V
    9. 6.9  Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter Architecture
      2. 7.3.2 External Reference
      3. 7.3.3 Output Buffers
      4. 7.3.4 Internal Power-On Reset (POR)
      5. 7.3.5 Temperature Drift and Calibration
      6. 7.3.6 DAC Output Deglitch Circuit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fast-Settling Mode and THD
      2. 7.4.2 DAC Update Rate Mode
    5. 7.5 Programming
      1. 7.5.1 Daisy-Chain Operation
      2. 7.5.2 CLR Pin Functionality and Software Clear
      3. 7.5.3 Output Update (Synchronous and Asynchronous)
        1. 7.5.3.1 Synchronous Update
        2. 7.5.3.2 Asynchronous Update
      4. 7.5.4 Software Reset Mode
    6. 7.6 Register Map
      1. 7.6.1 NOP Register (address = 00h) [reset = 0x000000h for bits [23:0]]
      2. 7.6.2 DAC-DATA Register (address = 01h) [reset = 0x000000h for bits [23:0]]
      3. 7.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]
      4. 7.6.4 DAC-CLEAR-DATA Register (address = 03h) [reset = 000000h for bits [23:0]]
      5. 7.6.5 TRIGGER Register (address = 04h) [reset = 000000h for bits [23:0]]
      6. 7.6.6 STATUS Register (address = 05h) [reset = 000000h for bits [23:0]]
      7. 7.6.7 CONFIG2 Register (address = 06h) [reset = 000040h for bits [23:0]]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Source Measure Unit (SMU)
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 High-Precision Control Loop
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Arbitrary Waveform Generation (AWG)
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Interfacing to a Processor
      2. 8.3.2 Interfacing to a Low-Jitter LDAC Source
      3. 8.3.3 Embedded Resistor Configurations
        1. 8.3.3.1 Minimizing Bias Current Mismatch
        2. 8.3.3.2 2x Gain Configuration
        3. 8.3.3.3 Generating Negative Reference
    4. 8.4 What to Do and What Not to Do
      1. 8.4.1 What to Do
      2. 8.4.2 What Not to Do
    5. 8.5 Initialization Set Up
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Supply Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Assembly Effects on Precision
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

9 Power Supply Recommendations

To get the best performance out of the DAC11001B, the power supply, grounding, and decoupling are very important. Use a PCB with a ground-plane reference, which helps in confining the digital return currents. A low mutual inductance path is created just beneath the high-frequency digital traces causing the return currents to follow the respective signal traces, thus minimizing crosstalk. On the other hand, dc signals spread over the ground plane without being confined below the signal trace. Therefore, in precision dc applications, limiting the common-impedance coupling is very difficult unless the ground planes are physically separated. Figure 9-1 shows a method to divide the grounds so that there is no common-mode current flow between the grounds, while maintaining the same dc potential across all grounds. This circuit assumes that the REFGND and LOAD-GND are provided from isolated power sources, therefore, there is no common-mode current flow through the reference or the load.

Figure 9-1 Power and Signal Grounding

When the load circuit is powered from a source referenced to AGND, and the LOAD-GND is shorted to AGND at the far end, the AGND-OUT must no longer be shorted to AGND locally near the DAC. The local shorting creates a ground loop, otherwise. The resulting connection that avoids the ground loop is shown in Figure 9-2.

Figure 9-2 Grounding Scheme When AGND is Load Ground

When the reference source is powered from a power source with AGND as the ground, there is a possibility of common-impedance coupling causing a code-dependent shift in the reference voltage. To avoid undesired coupling, drive REFGND using a buffer that maintains the reference ground potential equals to that of AGND-OUT, as shown in Figure 9-3.

Figure 9-3 Connecting the Reference Ground

Channel-to-channel dc crosstalk is a major concern in multichannel applications, such as battery test equipment. While the DAC11001B is single-channel, the crosstalk problem can appear at a system level when using multiple DAC11001B devices. The problem becomes severe when the grounds of the loads are shorted together creating a possible ground loop. In such cases, avoid the local short between AGND and AGND-OUT. Use a single short between AGND and DGND for all the DACs. If the PCB layout allows for the digital signal and analog power supplies to be kept separate, DGND and AGND can be combined to a single ground plane. Figure 9-4 shows an example circuit for minimizing dc crosstalk across DAC channels in a system.

Figure 9-4 Minimizing Multichannel DC Crosstalk

Power-supply bypassing and decoupling is key to keeping power supply noise, switching transients, and common-mode currents away from the DAC output. There are three main objective of power-supply bypassing:

  • Filtering: Filter out noise and ripple from power supplies
  • Bypassing: Supply switching or load transient currents locally by avoiding trace inductances
  • Decoupling: Stop local transient currents from impacting other circuits

To achieve these objectives, use the following 3-element scheme. Place a decoupling capacitor close to every power supply pin to provide the local current path for load and circuit switching transients. This capacitor must be referenced to the respective load ground for best load transient suppression. Use a 0.1-µF to 1-µF, X7R, multilayer ceramic capacitor (MLCC) for this purpose. For analog power supplies, a 10-Ω series resistor provides the best decoupling. For filtering the power-supply noise and ripple, 10-µF capacitors work best when placed at the power entry point of the board. An example decoupling scheme is shown in Figure 9-5.

GUID-844B80F4-9928-4E53-BB70-0AB5AA37F0C3-low.gif Figure 9-5 Power-Supply Decoupling