SLASF08A December 2021 – May 2024 DAC43508 , DAC53508 , DAC63508
PRODUCTION DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
X | DACn_DATA[11:0], DACn_DATA[9:0], DACn_DATA[7:0] | ||||||||||||||
W-0h | W-000h |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
15-12 | X | W | 0h | Don't care |
11-0 | DACn_DATA[11:0], DACn_DATA[9:0], DACn_DATA[7:0] |
W | 000h |
Writing to the DACn_DATA register forces the respective DAC channel to update the active register data to the DACn_DATA. Data are MSB-aligned in straight-binary format and follow the format below: DAC43508: { DATA[7:0], X, X, X, X } DAC53508: { DATA[9:0], X, X } DAC63508: { DATA[11:0] } X – Don’t care bits |