SLASF08A December 2021 – May 2024 DAC43508 , DAC53508 , DAC63508
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE | ||||||
Resolution | DAC63508 | 12 | Bits | |||
DAC53508 | 10 | |||||
DAC43508 | 8 | |||||
INL | Integral nonlinearity(1) | DAC53508, DAC43508 | –1 | 1 | LSB | |
DAC63508 | –4 | 4 | ||||
DNL | Differential nonlinearity(1) | –1 | 1 | LSB | ||
Zero-code error | Code 0d into DAC | 6 | 12 | mV | ||
Zero-code-error temperature coefficient | Code 0d into DAC | ±5 | µV/°C | |||
Offset error(1) | –0.5 | 0.25 | 0.5 | %FSR | ||
Offset-error temperature coefficient(1) | ±0.0003 | %FSR/°C | ||||
Gain error(1) | –0.5 | 0.25 | 0.5 | %FSR | ||
Gain-error temperature coefficient(1) | ±0.0004 | %FSR/°C | ||||
Full-scale error(4) | 2.7 V ≤ VDD ≤ 5.5 V | –0.5 | 0.25 | 0.5 | %FSR | |
1.8 V ≤ VDD ≤ 2.7 V | –1 | 0.5 | 1 | |||
Full-scale-error temperature coefficient(4) | ±0.0004 | %FSR/°C | ||||
OUTPUT | ||||||
VOUTX | Output voltage | 0 | VDD | V | ||
CL | Capacitive load(2) | RL = Infinite | 1 | nF | ||
2 | ||||||
Load regulation | DAC at midscale, ‒10 mA ≤ IOUT ≤ +10 mA, VDD = 5.5 V |
0.1 | mV/mA | |||
Short-circuit current(3) | VDD = 1.8 V | 10 | mA | |||
VDD = 2.7 V | 25 | |||||
VDD = 5.5 V | 50 | |||||
Output voltage headroom | To VDD, DAC output unloaded | 0.05 | V | |||
Output voltage headroom(2) | To VDD, load current = 10 mA at VDD = 5.5 V, load current = 3 mA at VDD = 2.7 V, load current = 1 mA at VDD = 1.8 V, DAC code at full-scale |
10 | %FSR | |||
ZO | DC output impedance | DAC at midscale | 0.25 | Ω | ||
DAC at code 32d | 0.25 | |||||
DAC at code 4064d | 0.26 | |||||
DC PSRR | Power supply rejection ratio (dc) | DAC at midscale, VDD = 5 V ±10% | 0.25 | mV/V | ||
DYNAMIC PERFORMANCE | ||||||
tsett | Output voltage settling time | 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V | 10 | µs | ||
SR | Slew rate | VDD = 5.5 V | 0.6 | V/µs | ||
Power-on glitch magnitude | 110 | mV | ||||
Vn | Output noise | f = 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V |
40 | µVpp | ||
Vn | Output noise | f = 0.1 Hz to 100 kHz, DAC at midscale, VDD = 5.5 V |
0.05 | mVrms | ||
Vn | Output noise density | f = 1 kHz, DAC at midscale, VDD = 5.5 V | 0.2 | µV/√Hz | ||
f = 10 kHz, DAC at midscale, VDD = 5.5 V | 0.2 | |||||
AC PSRR | Power-supply rejection ratio (ac) | 200-mV, 50-Hz or 60-Hz sine wave superimposed on power-supply voltage, DAC at midscale | –71 | dB | ||
Channel-to-channel ac crosstalk | Full-scale swing on adjacent channel | 1.5 | nV-s | |||
Channel-to-channel dc crosstalk | Full-scale swing on all channels, measured channel at zero-scale or full-scale |
0.2 | LSB | |||
Code change glitch impulse | ±1-LSB change around midscale (including feedthrough) | 10 | nV-s | |||
Code change glitch impulse magnitude | ±1-LSB change around midscale (including feedthrough) | 25 | mV | |||
VOLTAGE REFERENCE INPUT | ||||||
Reference input impedance | All channels powered on | 24 | kΩ | |||
Reference input capacitance | 50 | pF | ||||
DIGITAL INPUTS | ||||||
Digital feedthrough | SCLK = 1 MHz, DAC output static at midscale | 20 | nV-s | |||
Pin capacitance | Per pin | 10 | pF | |||
POWER | ||||||
IDD | Current flowing into VDD | Normal mode, all DACs at full-scale, digital interface static |
3 | 5 | mA | |
All DAC channels powered down | 50 | µA |