SLASF08A December 2021 – May 2024 DAC43508 , DAC53508 , DAC63508
PRODUCTION DATA
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
f(SCLK) | Serial clock frequency, 1.7 V ≤ VDD < 2.7 V | 25 | MHz | ||
Serial clock frequency, 2.7 V ≤ VDD ≤ 5.5 V | 50 | ||||
tSCLKHIGH | SCLK high time, 1.7 V ≤ VDD < 2.7 V | 20 | ns | ||
SCLK high time, 2.7 V ≤ VDD ≤ 5.5 V | 10 | ||||
tSCLKLOW | SCLK low time, 1.7 V ≤ VDD < 2.7 V | 20 | ns | ||
SCLK low time, 2.7 V ≤ VDD ≤ 5.5 V | 10 | ||||
tSDIS | SDI setup time, 1.7 V ≤ VDD < 2.7 V | 16 | ns | ||
SDI setup time, 2.7 V ≤ VDD ≤ 5.5 V | 8 | ||||
tSDIH | SDI hold time, 1.7 V ≤ VDD < 2.7 V | 10 | ns | ||
SDI hold time, 2.7 V ≤ VDD ≤ 5.5 V | 5 | ||||
tCSS | SYNC to SCLK falling edge setup time, 1.7 V ≤ VDD < 2.7 V | 36 | ns | ||
SYNC to SCLK falling edge setup time, 2.7 V ≤ VDD ≤ 5.5 V | 18 | ||||
tCSH | SCLK falling edge to SYNC rising edge, 1.7 V ≤ VDD < 2.7 V | 10 | ns | ||
SCLK falling edge to SYNC rising edge, 2.7 V ≤ VDD ≤ 5.5 V | 5 | ||||
tCSHIGH | SYNC high time, 1.7 V ≤ VDD < 2.7 V | 50 | ns | ||
SYNC high time, 2.7 V ≤ VDD ≤ 5.5 V | 25 |