SLASF27A December   2023  – November 2024 TAC5242

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 6.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hardware Control
      2. 7.3.2 Audio Serial Interfaces
        1. 7.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 7.3.2.2 Inter IC Sound (I2S) Interface
        3. 7.3.2.3 Left-Justified (LJ) Interface
      3. 7.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 7.3.4 Analog Input and Output Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 Integrated Microphone Bias
      7. 7.3.7 ADC Signal-Chain
        1. 7.3.7.1 Digital High-Pass Filter
        2. 7.3.7.2 Configurable Digital Decimation Filters
          1. 7.3.7.2.1 Linear-phase filters
            1. 7.3.7.2.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 7.3.7.2.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 7.3.7.2.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 7.3.7.2.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 7.3.7.2.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 7.3.7.2.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 7.3.7.2.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 7.3.7.2.2 Low-latency Filters
            1. 7.3.7.2.2.1 Sampling Rate: 24kHz or 22.05kHz
            2. 7.3.7.2.2.2 Sampling Rate: 32kHz or 29.4kHz
            3. 7.3.7.2.2.3 Sampling Rate: 48kHz or 44.1kHz
            4. 7.3.7.2.2.4 Sampling Rate: 96kHz or 88.2kHz
            5. 7.3.7.2.2.5 Sampling Rate: 192kHz or 176.4kHz
      8. 7.3.8 DAC Signal-Chain
        1. 7.3.8.1 Digital Interpolation Filters
          1. 7.3.8.1.1 Linear-phase filters
            1. 7.3.8.1.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 7.3.8.1.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 7.3.8.1.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 7.3.8.1.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 7.3.8.1.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 7.3.8.1.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 7.3.8.1.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 7.3.8.1.2 Low-latency Filters
            1. 7.3.8.1.2.1 Sampling Rate: 24kHz or 22.05kHz
            2. 7.3.8.1.2.2 Sampling Rate: 32kHz or 29.4kHz
            3. 7.3.8.1.2.3 Sampling Rate: 48kHz or 44.1kHz
            4. 7.3.8.1.2.4 Sampling Rate: 96kHz or 88.2kHz
            5. 7.3.8.1.2.5 Sampling Rate: 192kHz or 176.4kHz
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.1 Overview

The TAC5242 is from a scalable family of devices. As part of the extended family of devices, the TAC5242 consists of a high-performance, low-power, stereo, audio analog-to-digital converter (ADC) and audio digital-to-analog converter (DAC) with extensive feature integration. This device is optimized for various end-equipments and applications that require low-noise multichannel audio recording and playback and is intended for broad market applications such as ruggedized communication equipment, IP network cameras, professional audio, and multimedia applications. The high dynamic range of this device enables far-field audio recording with high fidelity. This device integrates a host of features that reduce cost, board space, and power consumption in space-constrained system designs. Package, performance, and compatible configuration across extended families make this device well-suited for scalable system designs.

The TAC5242 consists of the following blocks:

  • Pin or Hardware controlled device configurations
  • 2-channel, multi-bit, high-performance delta-sigma (ΔΣ) ADCs
  • Configurable single-ended or differential audio inputs
  • Low-noise microphone bias output

  • High-pass filter (HPF) with selectable cut-off frequency options on ADC signal path

  • 2-channel, multibit, high-performance delta-sigma (ΔΣ) DACs
  • Configurable single-ended, differential, or pseudo-differential audio outputs
  • Linear-phase or Low-latency digital decimation and interpolation filters
  • Integrated low-jitter, phase-locked loop (PLL) supporting a wide range of system clocks
  • Integrated digital and analog voltage regulators to support single-supply operation

The device supports a flexible audio serial interface [time-division multiplexing (TDM), I2S, or left-justified (LJ)] to transmit audio data seamlessly in the system across devices.