SLASF31A December   2023  – October 2024 TAD5242

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 5.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Hardware Control
      2. 6.3.2 Audio Serial Interfaces
        1. 6.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 6.3.2.2 Inter IC Sound (I2S) Interface
        3. 6.3.2.3 Left-Justified (LJ) Interface
      3. 6.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4 Analog Output Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 DAC Signal-Chain
        1. 6.3.6.1 Digital Interpolation Filters
          1. 6.3.6.1.1 Linear-phase filters
            1. 6.3.6.1.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 6.3.6.1.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 6.3.6.1.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 6.3.6.1.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 6.3.6.1.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 6.3.6.1.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 6.3.6.1.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 6.3.6.1.2 Low-latency Filters
            1. 6.3.6.1.2.1 Sampling Rate: 24kHz or 22.05kHz
            2. 6.3.6.1.2.2 Sampling Rate: 32kHz or 29.4kHz
            3. 6.3.6.1.2.3 Sampling Rate: 48kHz or 44.1kHz
            4. 6.3.6.1.2.4 Sampling Rate: 96kHz or 88.2kHz
            5. 6.3.6.1.2.5 Sampling Rate: 192kHz or 176.4kHz
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Performance Plots
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.2 Audio Serial Interfaces

Digital audio data flows between the host processor and the TAD5242 on the digital audio serial interface (ASI), or audio bus. This bus can be operated in target or controller mode through pin control. The ASI supports TDM, I2S and Left-Justified bus protocols. The data is in MSB-first, two's-complement pulse code modulation (PCM) format, with pin-selectable word-length configuration.

The device supports an audio bus controller or target mode of operation using the hardware pin MD0. In target mode, FSYNC and BCLK work as input pins whereas in controller mode, FSYNC and BCLK work as output pins generated by the device. Table 6-2 shows the controller and target mode selection using the MD0 pin.

Table 6-2 Controller and Target Mode Selection
MD0 CONTROLLER AND TARGET SELECTION
Short to Ground Target I2S Mode
Short to Ground with 4.7K Ohms Target TDM Mode
Short to AVDD Controller I2S Mode
Short to AVDD with 4.7K Ohms Controller TDM Mode
Short to AVDD with 22K Ohms Target LJ Mode
The word length for audio serial interface (ASI) in TAD5242 can be selected through MD1 and MD2 Pins in target mode of operation. The TAD5242 also supports 1.8V AVDD operation in target mode with 32-bit word length. Table 6-3 shows the configuration table for setting the word length, AVDD supply voltage and interpolation filter type applicable in Target Mode. In controller mode, AVDD supply mode is 3.3V, word length of 32-bits is supported, interpolation filter is configured in the linear-phase and the MD1 and MD2 Pins control the system clock configuration described in Table 6-8.
Table 6-3 Word Length, Supply Mode, and Interpolation Filter Selection
MD2 MD1 WORD LENGTH, SUPPLY MODE, AND INTERPOLATION FILTER SELECTION (Valid for Target Mode only)
Low Low AVDD=3.3V, Word Length=32, Linear-phase Filter
Low High AVDD=1.8V, Word Length=32, Linear-phase Filter
High Low AVDD=3.3V, Word Length=24, Linear-phase Filter
High High AVDD=3.3V, Word Length=32, Low-latency phase Filter

The TAD5242 also offers daisy chain option for TDM mode of operation. This option is auto enabled whenever device is selected to be in TDM Mode with MD0. MD6 Pin acts as a Daisy Chain output in this mode. In this case, for a TDM with N slots, the device plays the audio present on the last 2 slots, and the remaining slots are shifted to the right and sent on the MD6 pin, as shown in the block diagram in the Figure 6-2.

TAD5242 Daisy Chain in TDM Mode Block Diagram Figure 6-2 Daisy Chain in TDM Mode Block Diagram