SLASF31A December   2023  – October 2024 TAD5242

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 5.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Hardware Control
      2. 6.3.2 Audio Serial Interfaces
        1. 6.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 6.3.2.2 Inter IC Sound (I2S) Interface
        3. 6.3.2.3 Left-Justified (LJ) Interface
      3. 6.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4 Analog Output Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 DAC Signal-Chain
        1. 6.3.6.1 Digital Interpolation Filters
          1. 6.3.6.1.1 Linear-phase filters
            1. 6.3.6.1.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 6.3.6.1.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 6.3.6.1.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 6.3.6.1.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 6.3.6.1.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 6.3.6.1.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 6.3.6.1.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 6.3.6.1.2 Low-latency Filters
            1. 6.3.6.1.2.1 Sampling Rate: 24kHz or 22.05kHz
            2. 6.3.6.1.2.2 Sampling Rate: 32kHz or 29.4kHz
            3. 6.3.6.1.2.3 Sampling Rate: 48kHz or 44.1kHz
            4. 6.3.6.1.2.4 Sampling Rate: 96kHz or 88.2kHz
            5. 6.3.6.1.2.5 Sampling Rate: 192kHz or 176.4kHz
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Performance Plots
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

At TA = 25°C, AVDD = 3.3V, IOVDD = 3.3V, fIN = 1kHz sinusoidal signal, fS = 48kHz, 32-bit audio data, BCLK = 256 × fS, TDM target mode, and linear phase interpolation filter, with 1200Ω/600Ω line-out load in differential/single-ended configuration or 32Ω receiver differential load as applicable; measured filter free with an Audio Precision with a 20Hz to 20kHz un-weighted bandwidth, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DAC Performance for Line Output/Head Phone Playback
Full Scale Output Voltage Differential output between OUTxP and OUTxM, AVDD = 3.3V 2 VRMS
Differential output between OUTxP and OUTxM, AVDD = 1.8V 1
Single-ended output, AVDD = 3.3V 1
Single-ended output, AVDD = 1.8V 0.5
Pseudo-differential output between OUTxP and OUT1M with external common-mode sense, AVDD = 3.3V 1
Pseudo-differential output between OUTxP and OUT1M with external common-mode sense, AVDD = 1.8V 0.5
SNR Signal-to-noise ratio, A-weighted(1)(2) Differential output, 0dBFS Signal, AVDD = 3.3V 120 dB
Single-ended output, 0dBFS Signal, AVDD = 3.3V 111
Pseudo-differential output, 0dBFS Signal, AVDD = 3.3V 110
Differential output, 0dBFS Signal, AVDD = 1.8V 115
Single-ended output, 0dBFS Signal, AVDD = 1.8V 105
Pseudo-differential output, 0dBFS Signal, AVDD = 1.8V 104
DR Dynamic range, A-weighted(2) Differential output, –60dBFS Signal, AVDD = 3.3V 120 dB
Single-ended output, –60dBFS Signal, AVDD = 3.3V 111
Pseudo-differential output, –60dBFS Signal, AVDD = 3.3V 110
Differential output, –60dBFS Signal, AVDD = 1.8V 115
Single-ended output, –60dBFS Signal, AVDD = 1.8V 105
Pseudo-differential output, –60dBFS Signal, AVDD = 1.8V 104
THD+N Total harmonic distortion(2) Differential output, –1dBFS Signal, AVDD = 3.3V –100 dB
THD+N Total harmonic distortion(2) Single-ended output, –1dBFS Signal, AVDD = 3.3V –96 dB
Headphone Load Range(3) 8 16 300 Ω
Headphone/Line-out Cap Load 0 100 550 pF
Line-out Load Range 600 Ω
DAC Channel OTHER PARAMETERS
Output Offset 0 Input, Differential Line-output 0.5 mV
Output Common Mode Common Mode Level for OUTxP and OUTxM, AVDD = 1.8V 0.9 V
Output Common Mode Common Mode Level for OUTxP and OUTxM, AVDD = 3.3V 1.65 V
Common Mode Error DC Error in Common Mode Voltage ±10 mV
Output Signal Bandwidth 20 kHz
Input data word length Pin-selectable 24 32 Bits
Interchannel isolation –120 dB
Gain Error 0.1 dB
Interchannel gain mismatch 0.1 dB
Interchannel phase mismatch 1kHz sinusoidal signal 0.01 Degrees
PSRR Power-supply rejection ratio 100mVPP, 1kHz sinusoidal signal on AVDD, differential input, 0dB channel gain 120 dB
Pout Output Power Delivery Receiver/Headphone RL=16Ω, THD+N<1% in Differential or Pseudo-differential mode 62.5 mW
DIGITAL I/O
VIL Low-level digital input logic voltage threshold All digital pins, IOVDD 1.8V operation –0.3 0.35 x IOVDD V
All digital pins, IOVDD 3.3V operation –0.3 0.8
VIH High-level digital input logic voltage threshold All digital pins, IOVDD 1.8V operation 0.65 x IOVDD IOVDD + 0.3 V
All digital pins, IOVDD 3.3V operation 2 IOVDD + 0.3
VOL Low-level digital output voltage All digital pins, IOL = –2 mA, IOVDD 1.8V operation 0.45 V
All digital pins, IOL = –2 mA, IOVDD 3.3V operation 0.4
VOH High-level digital output voltage All digital pins, IOH = 2 mA, IOVDD 1.8V operation IOVDD – 0.45 V
All digital pins, IOH = 2 mA, IOVDD 3.3V operation 2.4
IIL Input logic-low leakage for digital inputs All digital pins, input = 0V –5 0.1 5 µA
IIH Input logic-high leakage for digital inputs All digital pins, input = IOVDD –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD Current consumption in sleep mode or low power mode All external clocks stopped with MD3 pin grounded, AVDD = 3.3V 0.8 mA
IIOVDD All external clocks stopped with MD3 pin grounded, IOVDD = 3.3V 0.6 µA
IIOVDD All external clocks stopped with MD3 pin grounded, IOVDD = 1.8V 0.2
IAVDD Current consumption with DAC to Headphone 2-channel operation at fS 16kHz, I2S Target Mode, BCLK = 64 × fS AVDD = 3.3V 16.3 mA
IIOVDD IOVDD = 3.3V 0.06
IIOVDD IOVDD = 1.8V 0.03
IAVDD Current consumption with DAC to Headphone 2-channel operation at fS 48kHz, I2S Target Mode, BCLK = 64 × fS AVDD = 3.3V 20 mA
IIOVDD IOVDD = 3.3V 0.06
IIOVDD IOVDD = 1.8V 0.03
IAVDD Current consumption with DAC to Line-out 2-channel operation at fS 16kHz, I2S Target Mode, BCLK = 64 × fS AVDD = 3.3V 17 mA
IAVDD Current consumption with DAC to Line-out 2-channel operation at fS 48kHz, I2S Target Mode, BCLK = 64 × fS AVDD = 3.3V 20 mA
IIOVDD IOVDD = 3.3V 0.06
IIOVDD IOVDD = 1.8V 0.03
(1) Ratio of output level with 1kHz full-scale sine-wave input, to the output level with no generator input signal and input shorted to ground, measured with an A-weighted filter over a 20Hz to 20kHz bandwidth
(2) All performance measurements done with 20kHz low-pass filter and, where noted, an A-weighted filter. Failure to use such a filter can result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, can affect dynamic specification values.
(3) For headphone loads <32Ω, input signal level should be limited as per the output power delivery specifications.