SLASF86B October   2023  – May 2024 MSPM0G3105-Q1 , MSPM0G3106-Q1 , MSPM0G3107-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Ramp
      1. 7.6.1 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
    13. 7.13 Typical Connection Diagram
    14. 7.14 Temperature Sensor
    15. 7.15 VREF
      1. 7.15.1 Voltage Characteristics
      2. 7.15.2 Electrical Characteristics
    16. 7.16 GPAMP
      1. 7.16.1 Electrical Characteristics
      2. 7.16.2 Switching Characteristics
    17. 7.17 I2C
      1. 7.17.1 I2C Timing Diagram
      2. 7.17.2 I2C Characteristics
      3. 7.17.3 I2C Filter
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 TRNG
      1. 7.21.1 TRNG Electrical Characteristics
      2. 7.21.2 TRNG Switching Characteristics
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G310x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 TRNG
    17. 8.17 AES
    18. 8.18 CRC
    19. 8.19 UART
    20. 8.20 I2C
    21. 8.21 SPI
    22. 8.22 CAN-FD
    23. 8.23 WWDT
    24. 8.24 RTC
    25. 8.25 Timers (TIMx)
    26. 8.26 Device Analog Connections
    27. 8.27 Input/Output Diagrams
    28. 8.28 Serial Wire Debug Interface
    29. 8.29 Bootstrap Loader (BSL)
    30. 8.30 Device Factory Constants
    31. 8.31 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.16.1 Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCM Common mode voltage range RRI = 0x0 -0.1 VDD-1 V
RRI = 0x1 1 VDD-0.2
RRI = 0x2 -0.1 VDD-0.2
Iq Quiescent current, per op-amp IO= 0mA, RRI = 0x0 97 µA
IO= 0mA, RRI = 0x1 or 0x2 93
GBW Gain-bandwidth product CL = 200pF 0.32 MHz
VOS Input offset voltage Noninverting, unity gain, TA = 25℃, VDD = 3.3V CHOP = 0x0 ±0.2 ±6.5 mV
CHOP = 0x1 ±0.08 ±0.4
dVOS/dT Input offset voltage temperature drift Noninverting, unity gain CHOP = 0x0 7.7 µV/°C
CHOP = 0x1 0.34
Ibias Input bias for muxed I/O pin at SoC 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOP=0x0 TA = 25°C ±40 pA
TA = 125°C ±4000
0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOP = 0x1  TA = 25°C ±200
TA = 125°C ±4000
CMRRDC Common mode rejection ratio, DC Over common mode voltage range CHOP = 0x0 48 77 dB
CHOP = 0x1  56 105
en Input voltage noise density Noninverting, unity gain f = 1kHz 43 nV/√Hz
en f = 10kHz 19
Rin Input resistance (1) 0.65 kΩ
Cin Input capacitance Common mode 4 pF
Differential 2
AOL Open-loop voltage gain, DC RL = 350kΩ, 0.3 < Vo < VDD-0.3 82 90 107 dB
PM phase margin CL = 200pF, RL= 350kΩ 69 70 72 degree
SR Slew rate Noninverting, unity gain, CL = 40pF 0.32 V/µs
THDN Total Harmonic Distortion + Noise 0.012 %
ILoad Output load current 4 mA
CLoad Output load capacitance 200 pF
(2) Rin here means the input resistance of mux in GPAMP.