SLASFC5 September   2024 TAS2320

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 Supply Voltage Monitors
      5. 6.4.5 Thermal Protection
      6. 6.4.6 Clocks and PLL
        1. 6.4.6.1 Auto clock based wakeup and clock errors
      7. 6.4.7 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Mono/Stereo Configuration
        2. 7.2.2.2 EMI Passive Devices
        3. 7.2.2.3 Miscellaneous Passive Devices
      3. 7.2.3 Application Performance Plots
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

6.4.3 Digital Audio Serial Interface

The device provides a flexible Audio Serial Interface (ASI) port. The port can be configured to support a variety of formats including stereo I2S, Left Justified, and TDM. Mono audio playback is available via the SDIN pin. The SDOUT pin is used to transmit sample streams including PVDD voltage, VBAT voltage, die temperature, status and audio for echo reference.

The TDM serial audio port supports up to 16 32-bit time slots at 44.1/48 kHz, 8 32-bit time slots at a 88.2/96 kHz sample rate and 4 32-bit time slots at a 176.4/192 kHz sample rate. The device supports 2 time slots at 32 bits in width and 4 or 8 time slots at 16, 24 or 32 bits in width. The device automatically detects the number of time slots and this does not need to be programmed. PCM data sampling rate and SBCLK to FSYNC ratio detected on the TDM bus is reported back on the read-only register bits FS_RATE_DETECTED[2:0] and FS_RATIO_DETECTED[3:0] respectively.

Table 6-23 PCM Data Sample Rate Detected
FS_RATE_DETECTED[2:0]

(Read Only)

 Setting
000 Reserved
001 14.7kHz / 16kHz
010 22.05kHz / 24kHz
011 29.4kHz / 32kHz
100 (default)

44.1kHz / 48kHz
101 88.2 kHz / 96 kHz
110 176.4 kHz / 192 kHz
111 Error condition
A frame begins with the transition of FSYNC from either high to low or low to high (set by the FRAME_START register bit). FSYNC and SDIN are sampled by SBCLK using either the rising or falling edge set by the RX_EDGE register bit. The RX_OFFSET[4:0] register bits define the number of SBCLK cycles from the transition of FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified format and 1 for an I2S format.

The RX_SLEN[1:0] register bits set the length of the RX time slot to 16, 24 or 32 (default) bits. The length of the audio sample word within the time slot is configured by the RX_WLEN[1:0] register bits. The RX port will left justify the audio sample within the time slot by default, but this can be changed to right justification via the RX_JUSTIFY register bit. The device supports mono and stereo down mix playback ([L+R]/2). By default the device will playback mono from the time slot equal to the I2C base address offset (set by the AD1 and AD2 pins) for playback. The RX_SCFG[1:0] register bits can be used to override the playback source to the left time slot, right time slot or stereo down mix set by the RX_SLOT_R[3:0] and RX_SLOT_L[3:0] register bits.

If time slot selection places reception either partially or fully beyond the frame boundary, the receiver returns a null sample equivalent to a digitally muted sample.

The TDM port can transmit a number of sample streams on the SDOUT pin including interrupts and status, PVDD voltage, VBAT voltage and die temperature.

Either the rising or falling edge of SBCLK can be used to transmit data on the SDOUT pin. This can be configured by setting the TX_EDGE register bit. The TX_OFFSET[2:0] register bits define the number SBCLK cycles between the start of a frame and the beginning of time slot 0. This is programmed to 0 for Left Justified format and 1 for I2S format. The TDM TX can either transmit logic 0 or Hi-Z depending on the setting of the TX_FILL register bit. An optional bus keeper can weakly hold the state of SDOUT pin when all devices are driving Hi-Z. Since only one bus keeper is required on SDOUT, this feature can be disabled via the TX_KEEPEN register bit. The bus keeper can be configured to hold the bus for only 1 LSB or Always (permanent) using TX_KEEPLN register bit. Additionally, the keeper LSB can be driven for a full cycle or half of cycle using TX_KEEPCY register bit.

The device also support monitoring and TDM transmit of PVDD and VBAT input voltages. For PVDD slot, enable and length settings PVDD_SLOT[5:0], PVDD_TX and PVDD_SLEN register bits can be use. Similarly for VBAT slot, enable and length settings VBAT_SLOT[5:0], VBAT_TX and VBAT_SLEN register bits can be used. Die temperature can also be transmitted from the device in same manner. Enable and slot settings for Die temperature are done using TEMP_TX and TEMP_SLOT [5:0] register bits.

Information about status of slots can be found in STATUS_SLOT[5:0] register bits. STATUS_TX register bit set high enables the status transmit. If time slot selections place transmission beyond the frame boundary, the transmitter will truncate transmission at the frame boundary.