SLASFD7 April 2024 TAS2505A-Q1
PRODUCTION DATA
The TAS2505A-Q1 has a built-in LDO which can generate the analog supply (AVDD) also the digital supply (DVDD) from input voltage range of 2.7V to 5.5V with high PSRR. If the combined power supply current is 50mA or less, then this LDO can deliver power to both analog and digital power supplies. If the only speaker power supply is present and the LDO Select pin is enabled, the LDO can power up without requiring other supplies. This LDO requires a minimum dropout voltage of 300mV and can support load currents up to 50mA. For stability reasons, the LDO requires a minimum decoupling capacitor of 1µF (±50%) on the analog supply (AVDD) pin and the digital supply (DVDD) pin. If this LDO output voltage for the digital supply (DVDD) pin, the analog supply (AVDD) pin connected to the digital supply (DVDD) externally is required.
The LDO is by default powered down for low sleep mode currents and can be enabled by driving the LDO_SELECT pin to SPKVDD (speaker power supply). When the LDO is disabled the AVDD pin is tri-stated and the device AVDD needs to be powered using an external supply. In that case, the DVDD pin is also tri-stated, and the device DVDD needs to be powered using an external supply. The output voltage of this LDO can be adjusted to a few different values as given in the Table 7-3.
Page-1, Register 2, D(5:4) | LDO Output |
---|---|
00 | 1.8V |
01 | 1.6V |
10 | 1.7V |
00 | 1.5V |
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).