SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
Table 22-3 lists the memory-mapped registers for the ADC10.
Address | Acronym | Register Name | Type | Reset | Section |
---|---|---|---|---|---|
1B0h | ADC10CTL0 | ADC10 control 0 | Read/write | 00h with POR | Section 22.4.1 |
1B2h | ADC10CTL1 | ADC10 control 1 | Read/write | 00h with POR | Section 22.4.2 |
4Ah | ADC10AE0 | ADC10 input enable 0 | Read/write | 00h with POR | Section 22.4.3 |
4Bh | ADC10AE1 | ADC10 input enable 1 | Read/write | 00h with POR | Section 22.4.4 |
1B4h | ADC10MEM | ADC10 memory | Read | Unchanged | Section 22.4.5 |
48h | ADC10DTC0 | ADC10 data transfer control 0 | Read/write | 00h with POR | Section 22.4.6 |
49h | ADC10DTC1 | ADC10 data transfer control 1 | Read/write | 00h with POR | Section 22.4.7 |
1BCh | ADC10SA | ADC10 data transfer start address | Read/write | 200h with POR | Section 22.4.8 |
ADC10 Control 0 Register
ADC10CTL0 is shown in Figure 22-17 and described in Table 22-4.
Return to Table 22-3.
ADC10 Control Register 0
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SREFx | ADC10SHTx | ADC10SR | REFOUT | REFBURST | |||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSC | REF2_5V | REFON | ADC10ON | ADC10IE | ADC10IFG | ENC | ADC10SC |
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
Can be modified only when ENC = 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | SREFx | R/W | 0h | Select reference. Can be modified only when ENC = 0. 000b = VR+ = VCC and VR- = VSS 001b = VR+ = VREF+ and VR- = VSS 010b = VR+ = VeREF+ and VR- = VSS. Devices with VeREF+ only. 011b = VR+ = Buffered VeREF+ and VR- = VSS. Devices with VeREF+ pin only. 100b = VR+ = VCC and VR- = VREF-/ VeREF-. Devices with VeREF- pin only. 101b = VR+ = VREF+ and VR- = VREF-/ VeREF-. Devices with VeREF+ and VeREF- pins only. 110b = VR+ = VeREF+ and VR- = VREF-/ VeREF-. Devices with VeREF+ and VeREF- pins only. 111b = VR+ = Buffered VeREF+ and VR- = VREF-/ VeREF-. Devices with VeREF+ and VeREF- pins only. |
12-11 | ADC10SHTx | R/W | 0h | ADC10 sample-and-hold time. 00b = 4 ADC10CLK cycles 01b = 8 ADC10CLK cycles 10b = 16 ADC10CLK cycles 11b = 64 ADC10CLK cycles |
10 | ADC10SR | R/W | 0h | ADC10 sampling rate. This bit selects the reference buffer drive capability for the maximum sampling rate. Setting ADC10SR reduces the current consumption of the reference buffer. Can be modified only when ENC = 0. 0b = Reference buffer supports up to approximately 200 ksps 1b = Reference buffer supports up to approximately 50 ksps |
9 | REFOUT | R/W | 0h | Reference output. 0b = Reference output off 1b = Reference output on. Devices with VeREF+ / VREF+ pin only. |
8 | REFBURST | R/W | 0h | Reference burst. Can be modified only when ENC = 0. 0b = Reference buffer on continuously 1b = Reference buffer on only during sample-and-conversion |
7 | MSC | R/W | 0h | Multiple sample and conversion. Valid only for sequence or repeated modes. Can be modified only when ENC = 0. 0b = The sampling requires a rising edge of the SHI signal to trigger each sample-and-conversion. 1b = The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed |
6 | REF2_5V | R/W | 0h | Reference-generator voltage. REFON must also be set. Can be modified only when ENC = 0. 0b = 1.5 V 1b = 2.5 V |
5 | REFON | R/W | 0h | Reference generator on. 0b = Reference off 1b = Reference on |
4 | ADC10ON | R/W | 0h | ADC10 on. 0b = ADC10 off 1b = ADC10 on |
3 | ADC10IE | R/W | 0h | ADC10 interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
2 | ADC10IFG | R/W | 0h | ADC10 interrupt flag. This bit is set if ADC10MEM is loaded with a conversion result. It is automatically reset when the interrupt request is accepted, or it may be reset by software. When using the DTC, this flag is set when a block of transfers is completed. 0b = No interrupt pending 1b = Interrupt pending |
1 | ENC | R/W | 0h | Enable conversion 0b = ADC10 disabled 1b = ADC10 enabled |
0 | ADC10SC | R/W | 0h | Start conversion. Software-controlled sample-and-conversion start. ADC10SC and ENC may be set together with one instruction. ADC10SC is reset automatically. 0b = No sample-and-conversion start 1b = Start sample-and-conversion |
ADC10 Control 1 Register
ADC10CTL1 is shown in Figure 22-18 and described in Table 22-5.
Return to Table 22-3.
ADC10 Control Register 1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INCHx | SHSx | ADC10DF | ISSH | ||||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC10DIVx | ADC10SSELx | CONSEQx | ADC10BUSY | ||||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | r-0 |
Can be modified only when ENC = 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | INCHx | R/W | 0h | Input channel select. These bits select the channel for a single-conversion or the highest channel for a sequence of conversions. Only available ADC channels should be selected. See the device-specific data sheet. Can be modified only when ENC = 0. 0000b = A0 0001b = A1 0010b = A2 0011b = A3 0100b = A4 0101b = A5 0110b = A6 0111b = A7 1000b = VeREF+ 1001b = VREF-/VeREF- 1010b = Temperature sensor 1011b = (VCC – VSS) / 2 1100b = (VCC – VSS) / 2, A12 on MSP430F22xx, MSP430G2x44, and MSP430G2x55 devices 1101b = (VCC – VSS) / 2, A13 on MSP430F22xx, MSP430G2x44, and MSP430G2x55 devices 1110b = (VCC – VSS) / 2, A14 on MSP430F22xx, MSP430G2x44, and MSP430G2x55 devices 1111b = (VCC – VSS) / 2, A15 on MSP430F22xx, MSP430G2x44, and MSP430G2x55 devices |
11-10 | SHSx | R/W | 0h | Sample-and-hold source select. Can be modified only when ENC = 0. 00b = ADC10SC bit 01b = Timer_A.OUT1#SLAU144ADC10694 10b = Timer_A.OUT0#SLAU144ADC10694 11b = Timer_A.OUT2 (Timer_A.OUT1 on MSP430F20x0, MSP430G2x31, and MSP430G2x30 devices)#SLAU144ADC10694 |
9 | ADC10DF | R/W | 0h | ADC10 data format. 0b = Straight binary 1b = 2s complement |
8 | ISSH | R/W | 0h | Invert signal sample-and-hold. 0b = The sample-input signal is not inverted. 1b = The sample-input signal is inverted. |
7-5 | ADC10DIVx | R/W | 0h | ADC10 clock divider. 000b = /1 001b = /2 010b = /3 011b = /4 100b = /5 101b = /6 110b = /7 111b = /8 |
4-3 | ADC10SSELx | R/W | 0h | ADC10 clock source select. 00b = ADC10OSC 01b = ACLK 10b = MCLK 11b = SMCLK |
2-1 | CONSEQx | R/W | 0h | Conversion sequence mode select 00b = Single-channel single-conversion mode 01b = Sequence-of-channels mode 10b = Repeat-single-channel mode 11b = Repeat-sequence-of-channels mode |
0 | ADC10BUSY | R | 0h | ADC10 busy. This bit indicates an active sample or conversion operation 0b = No operation is active. 1b = A sequence, sample, or conversion is active. |
ADC10 Input Enable 0 Register
ADC10AE0 is shown in Figure 22-19 and described in Table 22-6.
Return to Table 22-3.
Analog (Input) Enable Control Register 0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC10AE0x | |||||||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | ADC10AE0x | R/W | 0h | ADC10 analog enable. These bits enable the corresponding pin for analog input. Bit 0 corresponds to A0, Bit 1 corresponds to A1, and so on. The analog enable bit of not implemented channels should not be programmed to 1. 0b = Analog input disabled 1b = Analog input enabled |
ADC10 Input Enable 1 Register
ADC10AE1 is shown in Figure 22-20 and described in Table 22-7.
Return to Table 22-3.
Analog (Input) Enable Control Register 1 (MSP430F22xx, MSP430G2x44, and MSP430G2x55 Only)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC10AE1x | Reserved | ||||||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | ADC10AE1x | R/W | 0h | ADC10 analog enable. These bits enable the corresponding pin for analog input. Bit 4 corresponds to A12, Bit 5 corresponds to A13, Bit 6 corresponds to A14, and Bit 7 corresponds to A15. The analog enable bit of not implemented channels should not be programmed to 1. 0b = Analog input disabled 1b = Analog input enabled |
3-0 | Reserved | R | 0h | Reserved |
ADC10 Memory Register
ADC10MEM is shown in Figure 22-21 and described in Table 22-8.
Return to Table 22-3.
Conversion-Memory Register. This register is read as either right-justified straight-binary format or left-justified 2s-complement format, depending on the value of the ADC10DF bit in the ADC10CTL1 register.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Conversion_Results | |||||||
r0 | r0 | r0 | r0 | r0 | r0 | r | r |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Conversion_Results | |||||||
r | r | r | r | r | r | r | r |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | Conversion_Results | R | Unchanged | If ADC10DF = 0, the 10-bit conversion results are right-justified straight-binary format. Bit 9 is the MSB. 15-10 are always 0. If ADC10DF = 1, the 10-bit conversion results are left-justified 2s-complement format. Bit 15 is the MSB. Bits 5-0 are always 0. |
ADC10 Data Transfer Control 0 Register
ADC10DTC0 is shown in Figure 22-22 and described in Table 22-9.
Return to Table 22-3.
Data Transfer Control Register 0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | ADC10TB | ADC10CT | ADC10B1 | ADC10FETCH | |||
r0 | r0 | r0 | r0 | rw-(0) | rw-(0) | r-(0) | rw-(0) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | Reserved | R | 0h | Reserved. Always read as 0. |
3 | ADC10TB | R/W | 0h | ADC10 two-block mode
0b = One-block transfer mode 1b = Two-block transfer mode |
2 | ADC10CT | R/W | 0h | ADC10 continuous transfer
0b = Data transfer stops when one block (one-block mode) or two blocks (two-block mode) have completed. 1b = Data is transferred continuously. DTC operation is stopped only if ADC10CT cleared, or ADC10SA is written to. |
1 | ADC10B1 | R | 0h | ADC10 block one. This bit indicates for two-block mode which block is filled with ADC10 conversion results. ADC10B1 is valid only after ADC10IFG has been set the first time during DTC operation. ADC10TB must also be set. 0b = Block 2 is filled 1b = Block 1 is filled |
0 | ADC10FETCH | R/W | 0h | This bit should normally be reset. |
ADC10 Data Transfer Control 1 Register
ADC10DTC1 is shown in Figure 22-23 and described in Table 22-10.
Return to Table 22-3.
Data Transfer Control Register 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DTC Transfers | |||||||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DTC Transfers | R/W | 0h | DTC transfers. These bits define the number of transfers in each block.
0h = DTC is disabled 1h–FFh = Number of transfers per block |
ADC10 Data Transfer Start Address Register
ADC10SA is shown in Figure 22-24 and described in Table 22-11.
Return to Table 22-3.
Start Address Register for Data Transfer
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ADC10SAx | |||||||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC10SAx | Unused | ||||||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | r-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-1 | ADC10SAx | R/W | 0h | ADC10 start address. These bits are the start address for the DTC. A write to register ADC10SA is required to initiate DTC transfers. |
0 | Unused | R | 0h | Unused, Read only. Always read as 0. |