SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
Table 25-2 lists the memory-mapped registers for the DAC12.
Address | Acronym | Register Name | Type | Reset | Section |
---|---|---|---|---|---|
1C0h | DAC12_0CTL | DAC12_0 control | Read/write | 00h with POR | Section 25.4.1 |
1C8h | DAC12_0DAT | DAC12_0 data | Read/write | 00h with POR | Section 25.4.2 |
1C2h | DAC12_1CTL | DAC12_1 control | Read/write | 00h with POR | Section 25.4.1 |
1CAh | DAC12_1DAT | DAC12_1 data | Read/write | 00h with POR | Section 25.4.2 |
DAC12_x Control Register
DAC12_xCTL are shown in Figure 25-7 and described in Table 25-3.
Return to Table 25-2.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DAC12OPS | DAC12SREFx | DAC12RES | DAC12LSELx | DAC12CALON | DAC12IR | ||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC12AMPx | DAC12DF | DAC12IE | DAC12IFG | DAC12ENC | DAC12GRP | ||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
Can be modified only when DAC12ENC = 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | DAC12OPS | R/W | 0h | DAC12 output select. Can be modified only when DAC12ENC = 0. 0b = DAC12_0 output on P6.6, DAC12_1 output on P6.7 1b = DAC12_0 output on VeREF+, DAC12_1 output on P6.5 |
14-13 | DAC12SREFx | R/W | 0h | DAC12 select reference voltage. Can be modified only when DAC12ENC = 0. 00b = VREF+ 01b = VREF+ 10b = VeREF+ 11b = VeREF+ |
12 | DAC12RES | R/W | 0h | DAC12 resolution select. Can be modified only when DAC12ENC = 0. 0b = 12-bit resolution 1b = 8-bit resolution |
11-10 | DAC12LSELx | R/W | 0h | DAC12 load select. Selects the load trigger for the DAC12 latch. DAC12ENC must be set for the DAC to update, except when DAC12LSELx = 0. Can be modified only when DAC12ENC = 0. 00b = DAC12 latch loads when DAC12_xDAT written (DAC12ENC is ignored) 01b = DAC12 latch loads when DAC12_xDAT written, or, when grouped, when all DAC12_xDAT registers in the group have been written. 10b = Rising edge of Timer_A.OUT1 (TA1) 11b = Rising edge of Timer_B.OUT2 (TB2) |
9 | DAC12CALON | R/W | 0h | DAC12 calibration on. This bit initiates the DAC12 offset calibration sequence and is automatically reset when the calibration completes. 0b = Calibration is not active 1b = Initiate calibration or calibration in progress |
8 | DAC12IR | R/W | 0h | DAC12 input range. This bit sets the reference input and voltage output range. Can be modified only when DAC12ENC = 0. 0b = DAC12 full-scale output = 3x reference voltage 1b = DAC12 full-scale output = 1x reference voltage |
7-5 | DAC12AMPx | R/W | 0h | DAC12 amplifier setting. These bits select settling time vs current consumption for the DAC12 input and output amplifiers. See Table 25-4. Can be modified only when DAC12ENC = 0. |
4 | DAC12DF | R/W | 0h | DAC12 data format. Can be modified only when DAC12ENC = 0. 0b = Straight binary 1b = 2s complement |
3 | DAC12IE | R/W | 0h | DAC12 interrupt enable 0b = Disabled 1b = Enabled |
2 | DAC12IFG | R/W | 0h | DAC12 Interrupt flag 0b = No interrupt pending 1b = Interrupt pending |
1 | DAC12ENC | R/W | 0h | DAC12 enable conversion. This bit enables the DAC12 module when DAC12LSELx > 0. When DAC12LSELx = 0, DAC12ENC is ignored. 0b = DAC12 disabled 1b = DAC12 enabled |
0 | DAC12GRP | R/W | 0h | DAC12 group. Groups DAC12_x with the next higher DAC12_x. Not used for DAC12_1. 0b = Not grouped 1b = Grouped |
DAC12AMPx | Input Buffer | Output Buffer |
---|---|---|
000b | Off | DAC12 off, output high Z |
001b | Off | DAC12 off, output 0 V |
010b | Low speed and current | Low speed and current |
011b | Low speed and current | Medium speed and current |
100b | Low speed and current | High speed and current |
101b | Medium speed and current | Medium speed and current |
110b | Medium speed and current | High speed and current |
111b | High speed and current | High speed and current |
DAC12_x Data Register
DAC12_xDAT are shown in Figure 25-8 and described in Table 25-5.
Return to Table 25-2.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Reserved | DAC12 Data | ||||||
r(0) | r(0) | r(0) | r(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC12 Data | |||||||
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | Reserved | R | 0h | Unused. These bits are always 0 and do not affect the DAC12 core. |
11-0 | DAC12 Data | R/W | 0h | DAC12 data. See Table 25-6. |
DAC12 Data Format | DAC12 Data |
---|---|
12-bit binary | The DAC12 data are right justified. Bit 11 is the MSB. |
12-bit 2s complement | The DAC12 data are right justified. Bit 11 is the MSB (sign). |
8-bit binary | The DAC12 data are right justified. Bit 7 is the MSB. Bits 11-8 are don’t care and do not affect the DAC12 core. |
8-bit 2s complement | The DAC12 data are right justified. Bit 7 is the MSB (sign). Bits 11-8 are don’t care and do not affect the DAC12 core. |