SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
Table 14-1 lists the memory-mapped registers for the USI.
Address | Acronym | Register Name | Type | Reset | Section |
---|---|---|---|---|---|
78h | USICTL0 | USI control 0 | Read/write | 01h with PUC | Section 14.4.1 |
79h | USICTL1 | USI control 1 | Read/write | 01h with PUC | Section 14.4.2 |
7Ah | USICKCTL | USI clock control | Read/write | 00h with PUC | Section 14.4.3 |
7Bh | USICNT | USI bit counter | Read/write | 00h with PUC | Section 14.4.4 |
7Ch | USISRL | USI low byte shift | Read/write | Unchanged | Section 14.4.5 |
7Dh | USISRH | USI high byte shift | Read/write | Unchanged | Section 14.4.6 |
The USI registers can be accessed with word instructions as shown in Table 14-2.
Address | Acronym | Register Name | High-Byte Register | Low-Byte Register |
---|---|---|---|---|
078h | USICTL | USI control | USICTL1 | USICTL0 |
07Ah | USICCTL | USI clock and counter control | USICNT | USICKCTL |
07Ch | USISR | USI shift | USISRH | USISRL |
USI Control 0 Register
USICTL0 is shown in Figure 14-5 and described in Table 14-3.
Return to Table 14-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USIPE7 | USIPE6 | USIPE5 | USILSB | USIMST | USIGE | USIOE | USISWRST |
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | USIPE7 | R/W | 0h | USI SDI/SDA port enable. Input in SPI mode, input or open drain output in I2C mode. 0b = USI function disabled 1b = USI function enabled |
6 | USIPE6 | R/W | 0h | USI SDO/SCL port enable. Output in SPI mode, input or open drain output in I2C mode. 0b = USI function disabled 1b = USI function enabled |
5 | USIPE5 | R/W | 0h | USI SCLK port enable. Input in SPI slave mode, or I2C mode, output in SPI master mode. 0b = USI function disabled 1b = USI function enabled |
4 | USILSB | R/W | 0h | LSB first select. This bit controls the direction of the receive and transmit shift register. 0b = MSB first 1b = LSB first |
3 | USIMST | R/W | 0h | Master select 0b = Slave mode 1b = Master mode |
2 | USIGE | R/W | 0h | Output latch control 0b = Output latch enable depends on shift clock 1b = Output latch always enabled and transparent |
1 | USIOE | R/W | 0h | Data output enable 0b = Output disabled 1b = Output enabled |
0 | USISWRST | R/W | 1h | USI software reset 0b = USI released for operation 1b = USI logic held in reset state |
USI Control 1 Register
USICTL1 is shown in Figure 14-6 and described in Table 14-4.
Return to Table 14-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USICKPH | USII2C | USISTTIE | USIIE | USIAL | USISTP | USISTTIFG | USIIFG |
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | USICKPH | R/W | 0h | Clock phase select 0b = Data is changed on the first SCLK edge and captured on the following edge. 1b = Data is captured on the first SCLK edge and changed on the following edge. |
6 | USII2C | R/W | 0h | I2C mode enable 0b = I2C mode disabled 1b = I2C mode enabled |
5 | USISTTIE | R/W | 0h | START condition interrupt-enable 0b = Interrupt on START condition disabled 1b = Interrupt on START condition enabled |
4 | USIIE | R/W | 0h | USI counter interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
3 | USIAL | R/W | 0h | Arbitration lost 0b = No arbitration lost condition 1b = Arbitration lost |
2 | USISTP | R/W | 0h | STOP condition received. USISTP is automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0. 0b = No STOP condition received 1b = STOP condition received |
1 | USISTTIFG | R/W | 0h | START condition interrupt flag 0b = No START condition received. No interrupt pending. 1b = START condition received. Interrupt pending. |
0 | USIIFG | R/W | 1h | USI counter interrupt flag. Set when the USICNTx = 0. Automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0. 0b = No interrupt pending 1b = Interrupt pending |
USI Clock Control Register
USICKCTL is shown in Figure 14-7 and described in Table 14-5.
Return to Table 14-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USIDIVx | USISSELx | USICKPL | USISWCLK | ||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | USIDIVx | R/W | 0h | Clock divider select 000b = Divide by 1 001b = Divide by 2 010b = Divide by 4 011b = Divide by 8 100b = Divide by 16 101b = Divide by 32 110b = Divide by 64 111b = Divide by 128 |
4-2 | USISSELx | R/W | 0h | Clock source select. Not used in slave mode. 000b = SCLK (Not used in SPI mode) 001b = ACLK 010b = SMCLK 011b = SMCLK 100b = USISWCLK bit 101b = TACCR0 110b = TACCR1 111b = TACCR2 (Reserved on MSP430F20xx devices) |
1 | USICKPL | R/W | 0h | Clock polarity select 0b = Inactive state is low 1b = Inactive state is high |
0 | USISWCLK | R/W | 0h | Software clock 0b = Input clock is low 1b = Input clock is high |
USI Bit Counter Register
USICNT is shown in Figure 14-8 and described in Table 14-6.
Return to Table 14-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USISCLREL | USI16B | USIIFGCC | USICNTx | ||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | USISCLREL | R/W | 0h | SCL release. The SCL line is released from low to idle. USISCLREL is cleared if a START condition is detected. 0b = SCL line is held low if USIIFG is set 1b = SCL line is released |
6 | USI16B | R/W | 0h | 16-bit shift register enable 0b = 8-bit shift register mode. Low byte register USISRL is used. 1b = 16-bit shift register mode. Both high and low byte registers USISRL and USISRH are used. USISR addresses all 16 bits simultaneously. |
5 | USIIFGCC | R/W | 0h | USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be cleared automatically when USICNTx is written with a value > 0. 0b = USIIFG automatically cleared on USICNTx update 1b = USIIFG is not cleared automatically |
4-0 | USICNTx | R/W | 0h | USI bit count. The USICNTx bits set the number of bits to be received or transmitted. |
USI Low Byte Shift Register
USISRL is shown in Figure 14-9 and described in Table 14-7.
Return to Table 14-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USISRLx | |||||||
rw | rw | rw | rw | rw | rw | rw | rw |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | USISRLx | R/W | Unchanged | Contents of the USI low byte shift register |
USI High Byte Shift Register
USISRH is shown in Figure 14-10 and described in Table 14-8.
Return to Table 14-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USISRHx | |||||||
rw | rw | rw | rw | rw | rw | rw | rw |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | USISRHx | R/W | Unchanged | Contents of the USI high byte shift register. Ignored when USI16B = 0. |