SLAU319AF July   2010  – September 2022

 

  1.   Abstract - MSP430™ Flash Devices Bootloader (BSL)
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Supplementary Online Information
    2. 1.2 Overview of BSL Features
    3. 1.3 BSL Invocation
      1. 1.3.1 Hardware BSL Invocation
        1. 1.3.1.1 MSP430 Devices With Shared JTAG Pins
          1. 1.3.1.1.1 Factors That Prevent BSL Invocation With Shared JTAG Pins
        2. 1.3.1.2 MSP430 Flash Devices With Dedicated JTAG Pins
          1. 1.3.1.2.1 Factors That Prevent BSL Invocation With Dedicated JTAG Pins
        3. 1.3.1.3 Devices With USB
      2. 1.3.2 Software BSL Invocation
    4. 1.4 UART Protocol
    5. 1.5 USB Protocol
  4. 2Bootloader Protocol – 1xx, 2xx, and 4xx Families
    1. 2.1 Synchronization Sequence
    2. 2.2 Commands
      1. 2.2.1 Unprotected Commands
      2. 2.2.2 Password Protected Commands
    3. 2.3 Programming Flow
    4. 2.4 Data Frame
      1. 2.4.1 Data-Stream Structure
      2. 2.4.2 Checksum
      3. 2.4.3 Example Sequence
      4. 2.4.4 Commands – Detailed Description
        1. 2.4.4.1  General
        2. 2.4.4.2  RX Data Block
        3. 2.4.4.3  RX Password
        4. 2.4.4.4  Mass Erase
        5. 2.4.4.5  Erase Segment
        6. 2.4.4.6  Erase Main or Info
        7. 2.4.4.7  Erase Check
        8. 2.4.4.8  Change Baud Rate
        9. 2.4.4.9  Set Memory Offset
        10. 2.4.4.10 Load PC
        11. 2.4.4.11 TX Data Block
        12. 2.4.4.12 TX BSL Version
    5. 2.5 Loadable BSL
    6. 2.6 Exiting the BSL
    7. 2.7 Password Protection
    8. 2.8 Code Protection Fuse
    9. 2.9 BSL Internal Settings and Resources
      1. 2.9.1 Chip Identification and BSL Version
      2. 2.9.2 Vectors to Call the BSL Externally
      3. 2.9.3 Initialization Status
      4. 2.9.4 Memory Allocation and Resources
  5. 3Bootloader Protocol – F5xx and F6xx Families
    1. 3.1 BSL Data Packet
    2. 3.2 UART Peripheral Interface (PI)
      1. 3.2.1 Wrapper
      2. 3.2.2 Abbreviations
      3. 3.2.3 Messages
      4. 3.2.4 Interface Specific Commands
        1. 3.2.4.1 Change Baud Rate
    3. 3.3 I2C Peripheral Interface
      1. 3.3.1 I2C Protocol Definition
      2. 3.3.2 Basic Protocol With Byte Level Acknowledge
      3. 3.3.3 I2C Protocol for BSL - Read From Slave
      4. 3.3.4 Acknowledge (ACK)
      5. 3.3.5 Wrapper
    4. 3.4 USB Peripheral Interface
      1. 3.4.1 Wrapper
      2. 3.4.2 Hardware Requirements
    5. 3.5 BSL Core Command Structure
      1. 3.5.1 Abbreviations
      2. 3.5.2 Command Descriptions
    6. 3.6 BSL Security
      1. 3.6.1 Protected Commands
      2. 3.6.2 RAM Erase
    7. 3.7 BSL Core Responses
      1. 3.7.1 Abbreviations
      2. 3.7.2 BSL Core Messages
      3. 3.7.3 BSL Version Number
      4. 3.7.4 Example Sequences for UART BSL
    8. 3.8 BSL Public Functions and Z-Area
      1. 3.8.1 Starting the BSL From an External Application
      2. 3.8.2 Return to BSL Function Description
  6. 4Bootloader Hardware
    1. 4.1 Hardware Description
      1. 4.1.1 Power Supply
      2. 4.1.2 Serial Interface
        1. 4.1.2.1 Level Shifting
        2. 4.1.2.2 Control of RST/NMI and TEST or TCK Pins
      3. 4.1.3 Target Connector
      4. 4.1.4 Parts List
  7. 5Differences Between Devices and Bootloader Versions
    1. 5.1 1xx, 2xx, and 4xx BSL Versions
    2. 5.2 Special Consideration for ROM BSL Version 1.10
    3. 5.3 1xx, 2xx, and 4xx BSL Known Issues
    4. 5.4 Special Note on the MSP430F14x Device Family BSL
    5. 5.5 F5xx and F6xx Flash-Based BSL Versions
  8. 6Bootloader PCB Layout Suggestion
  9. 7Revision History

5.5 F5xx and F6xx Flash-Based BSL Versions

Table 5-9
Devices MSP430F5438, MSP430F5437, MSP430F5435, MSP430F5436, MSP430F5435, MSP430F5419, MSP430F5418
BSL Version 00.01.01.01
RAM Erased None
Buffer Size for Core Commands 260 bytes
Notable Information
  1. UART TX and RX BSL pins are noted in the device data sheet
  2. Due to the known errata SYS4 and FLASH32, BSL is not reprogrammable.
  3. However, the JTAGLOCK KEY (which resided on the BSL area) can still be programmed through BSL itself. Note that this leads to the ability to lock and unlock JTAG one time. Locking JTAG is performed by writing 0x5555 to the JTAGLOCK KEY, and unlocking JTAG is performed by writing 0x0000. Once this is done, there is no chance to lock back the JTAG, as it needs the entire BSL programming.
  4. The only supported baud rates are 9600 and 57600.
  5. The BSL transmits on TA0.0 and receives on TA0.1.
  6. The BSL does not expect a parity bit.
Known Bugs
  1. The password for the BSL is the bytes between addresses 0xFFF0 and 0xFFFF. This means that this BSL version expects only 16 bytes for a password in the RX Password command. Sending 32 bytes returns an error.
  2. If the address 0x20396 or 0x20397 is included in the address range of the CRC command, the returned data is incorrect.
  3. The Mass Erase command also erases Info_A.
  4. On incorrect password, the device erases all RAM, including its stack. Thus, proper return of an error code is not assured.
  5. The total number of bytes for the CRC function is masked with 0x7FFF and is, therefore, limited to 32767.
Table 5-10
Devices MSP430F5438A, MSP430F5437A, MSP430F5435A, MSP430F5436A, MSP430F5435A, MSP430F5419A, MSP430F5418A
BSL Version 00.05.04.03 (Rev A to Rev E)
00.07.05.04 (Rev F and later)
RAM Erased 0x1C00 to 0x5BFF
Buffer Size for Core Commands 260 bytes
Notable Information
  1. UART TX and RX BSL pins are noted in the device data sheet
Known Bugs
  1. The baud rate of 115k cannot be ensured across all clock, voltage, and temperature variations.
Table 5-11
Devices CC430F6147, CC430F6145, CC430F6143, CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125, CC430F5147, CC430F5145, CC430F5143, CC430F5137, CC430F5135, CC430F5133, CC430F5125, CC430F5123
BSL Version 00.05.04.52 (Rev A to Rev C)
00.07.05.53 (Rev D and later)
RAM Erased 0x1C00 to 0x23FF
Buffer Size for Core Commands 260 bytes
Notable Information
  1. UART TX and RX BSL pins are implemented on pin P1.6 (TXD) and P1.5 (RXD)
Known Bugs
  1. The baud rate of 115k cannot be ensured across all clock, voltage, and temperature variations.
Table 5-12
Devices MSP430F5510, MSP430F5500, MSP430F5501, MSP430F5502, MSP430F5503, MSP430F5504, MSP430F5505, MSP430F5506, MSP430F5507, MSP430F5508, MSP430F5509
BSL Version 00.03.83.33 (Rev A to Rev E)
00.07.88.38 (Rev F until May 2015)
00.08.88.39 (Rev F and later)
RAM Erased 0x2400 to 0x33FF
Buffer Size for Core Commands 62 bytes
Notable Information
  1. Device is programmed with the factory USB BSL.
  2. Factory USB BSL is RAM write only. Full BSL must first be loaded into device RAM and started to perform flash write. Only the commands RX PASSWORD, RX DATA BLOCK FAST, and SET PC are supported.
  3. When starting this BSL from an application, the application should first de-enumerate itself, then delay (approximately 500 ms) before starting the BSL. This allows proper re-enumeration with the host.
  4. External crystal at XT2 is required to ensure USB operation.
Known Bugs The USB module is not correctly locked by the BSL. For legacy reasons this behavior is kept.
Table 5-13
Devices MSP430F5529, MSP430F5513, MSP430F5514, MSP430F5515, MSP430F5517, MSP430F5519, MSP430F5521, MSP430F5522, MSP430F5524, MSP430F5525, MSP430F5526, MSP430F5527, MSP430F5528
BSL Version 00.03.83.33 (Rev A to Rev H)
00.07.85.36 (Rev I)
00.07.87.37 (Rev J)
00.07.88.38 (Rev K until May 2015)
00.08.88.39 (Rev K and later)
RAM Erased 0x2400 to 0x33FF
Buffer Size for Core Commands 62 bytes
Notable Information
  1. Device is programmed with the factory USB BSL.
  2. Factory USB BSL is RAM write only. Full BSL must first be loaded into device RAM and started to perform flash write. Only the commands RX PASSWORD, RX DATA BLOCK FAST, and SET PC are supported.
  3. When starting this BSL from an application, the application should first de-enumerate itself, then delay (approximately 500 ms) before starting the BSL. This allows proper re-enumeration with the host.
  4. External crystal at XT2 is required to ensure USB operation.
Known Bugs The USB module is not correctly locked by the BSL. For legacy reasons this behavior is kept.
Table 5-14
Devices MSP430F5172, MSP430F5152, MSP430F5132, MSP430F5171, MSP430F5151, MSP430F5131
BSL Version 00.07.05.04
RAM Erased 0x1C00 to 0x1FFF
Buffer Size for Core Commands 260 bytes
Notable Information
  1. UART TX and RX BSL pins are noted in the device data sheet
Known Bugs
  1. The baud rate of 115k cannot be ensured across all clock, voltage, and temperature variations.
Table 5-15
Devices MSP430F5229, MSP430F5227, MSP430F5219, MSP430F5217, MSP430F5224, MSP430F5222, MSP430F5213, MSP430F5212
BSL Version 00.07.05.04
RAM Erased 0x2400 to 0x43FF
Buffer Size for Core Commands 260 bytes
Notable Information
  1. UART TX and RX BSL pins are noted in the device data sheet
Known Bugs
  1. The baud rate of 115k cannot be ensured across all clock, voltage, and temperature variations.
Table 5-16
Devices MSP430F5249, MSP430F5247, MSP430F5244, MSP430F5242, MSP430F5239, MSP430F5237, MSP430F5234, MSP430F5232
BSL Version 00.08.08.04
RAM Erased 0x2400 to 0x43FF
Buffer Size for Core Commands 260 bytes
Notable Information
  1. UART TX and RX BSL pins are noted in the device data sheet
Known Bugs
  1. The baud rate of 115k cannot be ensured across all clock, voltage, and temperature variations.
Table 5-17
Devices MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
BSL Version 00.08.08.04
RAM Erased 0x2400 to 0x43FF
Buffer Size for Core Commands 260 bytes
Notable Information
  1. UART TX and RX BSL pins are noted in the device data sheet
  2. A BSL firmware image that uses pins in the DVIO supply domain is available for download in the custom BSL package.
Known Bugs
  1. The baud rate of 115k cannot be ensured across all clock, voltage, and temperature variations.
Table 5-18
Devices MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
BSL Version 00.07.06.94
RAM erased 0x1C00 to 0x23FF
Buffer size for Core Commands 260 bytes
Notable Information
  1. I2C pins are noted in the device data sheet
Known Bugs
  1. I2C read commands with length greater than 260 do not return correct data.
Table 5-19
Devices MSP430F5310, MSP430F5309, MSP430F5308, MSP430F5304, MSP430F5340, MSP430F5341, MSP430F5342, MSP430F5329, MSP430F5324, MSP430F5325, MSP430F5326, MSP430F5327, MSP430F5328
BSL Version 00.06.04.04
RAM Erased 0x1C00 to 0x33FF
Buffer Size for Core Commands 260 bytes
Notable Information
  1. UART TX and RX BSL pins are noted in the device data sheet
Known Bugs
  1. The baud rate of 115k cannot be ensured across all clock, voltage, and temperature variations.
Table 5-20
Devices MSP430F6638, MSP430F6637, MSP430F6636, MSP430F6635, MSP430F6634, MSP430F6633, MSP430F6632, MSP430F6631, MSP430F6630, MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635, MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630
BSL Version 00.04.84.34 (Rev A to Rev D)
00.08.88.38 (Rev E until May 2015)
00.08.88.39 (Rev E and later)
RAM erased 0x2400 to 0x33FF
Buffer Size for Core Commands 62 bytes
Notable Information
  1. Device is programmed with the factory USB BSL.
  2. Factory USB BSL is RAM write only. Full BSL must first be loaded into device RAM and started to perform flash write. Only the commands RX PASSWORD, RX DATA BLOCK FAST, and SET PC are supported
  3. When starting this BSL from an application, the application should first de-enumerate itself, then delay (approximately 500 ms) before starting the BSL. This allows proper re-enumeration with the host.
Known Bugs The USB module is not correctly locked by the BSL. For legacy reasons this behavior is kept.
Table 5-21
Devices MSP430F6659, MSP430F6658, MSP430F5659, MSP430F5658
BSL Version 00.07.86.36 (Rev A)
00.08.88.38 (Rev B until May 2015)
00.08.88.39 (Rev B and later)
RAM Erased 0x2400 to 0x33FF
Buffer Size for Core Commands 62 bytes
Notable Information
  1. Device is programmed with the factory USB BSL.
  2. Factory USB BSL is RAM write only. Full BSL must first be loaded into device RAM and started to perform flash write. Only the commands RX PASSWORD, RX DATA BLOCK FAST, and SET PC are supported
  3. When starting this BSL from an application, the application should first de-enumerate itself, then delay (approximately 500 ms) before starting the BSL. This allows proper re-enumeration with the host.
Known Bugs
Table 5-22
Devices MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433, MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333, MSP430F6459, MSP430F6458, MSP430F5359, MSP430F5358
BSL Version 00.07.05.04
RAM Erased 0x1C00 to 0x43FF
Buffer Size for Core Commands 260 bytes
Notable Information
  1. UART TX and RX BSL pins are noted in the device data sheet
Known Bugs
  1. The baud rate of 115k cannot be ensured across all clock, voltage, and temperature variations.
Table 5-23
Devices MSP430F6736, MSP430F6720, MSP430F6721, MSP430F6723, MSP430F6724, MSP430F6725, MSP430F6726, MSP430F6730, MSP430F6731, MSP430F6733, MSP430F6734, MSP430F6735, MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A, MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A, MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
BSL Version 00.07.05.04
RAM Erased 0x1C00 to 0x1FFF
Buffer Size for Core Commands 260 bytes
Notable Information
  1. UART TX and RX BSL pins are noted in the device data sheet
Known Bugs
  1. The baud rate of 115k cannot be ensured across all clock, voltage, and temperature variations.
Table 5-24
Devices MSP430F6779, MSP430F6745, MSP430F6746, MSP430F6747, MSP430F6748, MSP430F6749, MSP430F6765, MSP430F6776, MSP430F6767, MSP430F6768, MSP430F6769, MSP430F6775, MSP430F6776, MSP430F6777, MSP430F6778, MSP430F67791, MSP430F67451, MSP430F67461, MSP430F67471, MSP430F67481, MSP430F67491, MSP430F67651, MSP430F67761, MSP430F67671, MSP430F67681, MSP430F67691, MSP430F67751, MSP430F67761, MSP430F67771, MSP430F67781
BSL Version 00.07.05.04
RAM Erased 0x1C00 to 0x5BFF
Buffer Size for Core Commands 260 bytes
Notable Information
  1. UART TX and RX BSL pins are noted in the device data sheet
Known Bugs
  1. The baud rate of 115k cannot be ensured across all clock, voltage, and temperature variations.
Table 5-25
Devices MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A, MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A MSP430F6749A, MSP430F6748A, MSP430F6747A MSP430F6746A MSP430F6745A, MSP430F67791A, MSP430F67781A, MSP430F67771A, MSP430F67761A, MSP430F67751A, MSP430F67691A, MSP430F67681A, MSP430F67671A, MSP430F67661A, MSP430F67651A, MSP430F67491A, MSP430F67481A, MSP430F67471A, MSP430F67461A, MSP430F67451A
BSL Version 00.07.05.04
RAM Erased 0x1C00 to 0x5BFF
Buffer Size for Core Commands 260 bytes
Notable Information
  1. UART TX and RX BSL pins are noted in the device data sheet
Known Bugs
  1. The baud rate of 115k cannot be ensured across all clock, voltage, and temperature variations.
Table 5-26
Devices MSP430F67641, MSP430F67621
BSL Version 00.07.05.04
RAM Erased 0x1C00 to 0x1FFF
Buffer Size for Core Commands 260 bytes
Notable Information
  1. UART TX and RX BSL pins are noted in the device data sheet
Known Bugs
  1. The baud rate of 115k cannot be ensured across all clock, voltage, and temperature variations.
Table 5-27
Devices MSP430FG6426, MSP430FG6425
BSL Version 00.08.08.04
RAM Erased 0x1C00 to 0x43FF
Buffer Size for Core Commands 260 bytes
Notable Information
  1. UART TX and RX BSL pins are noted in the device data sheet
Known Bugs
  1. The baud rate of 115k cannot be ensured across all clock, voltage, and temperature variations.
Table 5-28
Devices MSP430FG6626, MSP430FG6625
BSL Version 00.08.88.38
RAM Erased 0x1C00 to 0x43FF
Buffer Size for Core Commands 260 bytes
Notable Information
  1. Device is programmed with the factory USB BSL.
  2. Factory USB BSL is RAM write only. Full BSL must first be loaded into device RAM and started to perform flash write. Only the commands RX PASSWORD, RX DATA BLOCK FAST, and SET PC are supported
  3. When starting this BSL from an application, the application should first de-enumerate itself, then delay (approximately 500 ms) before starting the BSL. This allows proper re-enumeration with the host.
  4. External crystal at XT2 is required to ensure USB operation.
Known Bugs