SLAU319AF July   2010  – September 2022

 

  1.   Abstract - MSP430™ Flash Devices Bootloader (BSL)
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Supplementary Online Information
    2. 1.2 Overview of BSL Features
    3. 1.3 BSL Invocation
      1. 1.3.1 Hardware BSL Invocation
        1. 1.3.1.1 MSP430 Devices With Shared JTAG Pins
          1. 1.3.1.1.1 Factors That Prevent BSL Invocation With Shared JTAG Pins
        2. 1.3.1.2 MSP430 Flash Devices With Dedicated JTAG Pins
          1. 1.3.1.2.1 Factors That Prevent BSL Invocation With Dedicated JTAG Pins
        3. 1.3.1.3 Devices With USB
      2. 1.3.2 Software BSL Invocation
    4. 1.4 UART Protocol
    5. 1.5 USB Protocol
  4. 2Bootloader Protocol – 1xx, 2xx, and 4xx Families
    1. 2.1 Synchronization Sequence
    2. 2.2 Commands
      1. 2.2.1 Unprotected Commands
      2. 2.2.2 Password Protected Commands
    3. 2.3 Programming Flow
    4. 2.4 Data Frame
      1. 2.4.1 Data-Stream Structure
      2. 2.4.2 Checksum
      3. 2.4.3 Example Sequence
      4. 2.4.4 Commands – Detailed Description
        1. 2.4.4.1  General
        2. 2.4.4.2  RX Data Block
        3. 2.4.4.3  RX Password
        4. 2.4.4.4  Mass Erase
        5. 2.4.4.5  Erase Segment
        6. 2.4.4.6  Erase Main or Info
        7. 2.4.4.7  Erase Check
        8. 2.4.4.8  Change Baud Rate
        9. 2.4.4.9  Set Memory Offset
        10. 2.4.4.10 Load PC
        11. 2.4.4.11 TX Data Block
        12. 2.4.4.12 TX BSL Version
    5. 2.5 Loadable BSL
    6. 2.6 Exiting the BSL
    7. 2.7 Password Protection
    8. 2.8 Code Protection Fuse
    9. 2.9 BSL Internal Settings and Resources
      1. 2.9.1 Chip Identification and BSL Version
      2. 2.9.2 Vectors to Call the BSL Externally
      3. 2.9.3 Initialization Status
      4. 2.9.4 Memory Allocation and Resources
  5. 3Bootloader Protocol – F5xx and F6xx Families
    1. 3.1 BSL Data Packet
    2. 3.2 UART Peripheral Interface (PI)
      1. 3.2.1 Wrapper
      2. 3.2.2 Abbreviations
      3. 3.2.3 Messages
      4. 3.2.4 Interface Specific Commands
        1. 3.2.4.1 Change Baud Rate
    3. 3.3 I2C Peripheral Interface
      1. 3.3.1 I2C Protocol Definition
      2. 3.3.2 Basic Protocol With Byte Level Acknowledge
      3. 3.3.3 I2C Protocol for BSL - Read From Slave
      4. 3.3.4 Acknowledge (ACK)
      5. 3.3.5 Wrapper
    4. 3.4 USB Peripheral Interface
      1. 3.4.1 Wrapper
      2. 3.4.2 Hardware Requirements
    5. 3.5 BSL Core Command Structure
      1. 3.5.1 Abbreviations
      2. 3.5.2 Command Descriptions
    6. 3.6 BSL Security
      1. 3.6.1 Protected Commands
      2. 3.6.2 RAM Erase
    7. 3.7 BSL Core Responses
      1. 3.7.1 Abbreviations
      2. 3.7.2 BSL Core Messages
      3. 3.7.3 BSL Version Number
      4. 3.7.4 Example Sequences for UART BSL
    8. 3.8 BSL Public Functions and Z-Area
      1. 3.8.1 Starting the BSL From an External Application
      2. 3.8.2 Return to BSL Function Description
  6. 4Bootloader Hardware
    1. 4.1 Hardware Description
      1. 4.1.1 Power Supply
      2. 4.1.2 Serial Interface
        1. 4.1.2.1 Level Shifting
        2. 4.1.2.2 Control of RST/NMI and TEST or TCK Pins
      3. 4.1.3 Target Connector
      4. 4.1.4 Parts List
  7. 5Differences Between Devices and Bootloader Versions
    1. 5.1 1xx, 2xx, and 4xx BSL Versions
    2. 5.2 Special Consideration for ROM BSL Version 1.10
    3. 5.3 1xx, 2xx, and 4xx BSL Known Issues
    4. 5.4 Special Note on the MSP430F14x Device Family BSL
    5. 5.5 F5xx and F6xx Flash-Based BSL Versions
  8. 6Bootloader PCB Layout Suggestion
  9. 7Revision History

2.4.1 Data-Stream Structure

  • The first eight bytes (HDR through LH) are mandatory (xx represents dummy data).
  • Data bytes D1 to Dn are optional.
  • Two bytes (CKL and CKH) for checksum are mandatory.
  • Acknowledge done by the BSL is mandatory, except with the TX data block and TX BSL version commands.
Table 2-1 Data Frame of BSL Commands(1)(3)(6)
Received BSL Command HDR CMD L1 L2 AL AH LL LH D1 D2…Dn CKL CKH ACK(2)
RX data block 80 12 n n AL AH n–4 0 D1 D2 … Dn–4 CKL CKH ACK
RX password 80 10 24 24 xx xx xx xx D1 D2 … D20 CKL CKH ACK
Erase segment 80 16 04 04 AL AH 02 A5 – – – – CKL CKH ACK
Erase main or info 80 16 04 04 AL AH 04 A5 – – – – CKL CKH ACK
Mass erase 80 18 04 04 xx xx 06 A5 – – – – CKL CKH ACK
Erase check(4) 80 1C 04 04 AL AH LL LH – – – – CKL CKH ACK
Change baud rate(5) 80 20 04 04 D1 D2 D3 xx – – – – CKL CKH ACK
Set mem offset 80 21 04 04 xx xx AL AH – – – – CKL CKH ACK
Load PC 80 1A 04 04 AL AH xx xx – – – – CKL CKH ACK
TX data block 80 14 04 04 AL AH n 0 – – – – CKL CKH –
BSL responds 80 xx n n D1 D2 ... ... … ... … Dn CKL CKH –
TX BSL version(4) 80 1E 04 04 xx xx xx xx – – – – CKL CKH –
BSL responds 80 xx 10 10 D1 D2 ... ... … … … D10 CKL CKH –
(1) All numbers are bytes in hexadecimal notation.
(2) ACK is sent back by the BSL.
(3) The synchronization sequence is not part of the data frame.
(4) The erase check and TX BSL version commands are members of the standard command set in BSLs V1.50 or higher but excluding 2.x BSLs.
(5) The change baud rate command is not a member of the standard command set (it is available in V1.60 or higher or in loadable BL_150S_14x.txt).
(6) Abbreviations:
HDR: Header. Any value between 80h and 8Fh (normally 80h).
CMD: Command identification
L1, L2: Number of bytes consisting of AL through Dn. Restrictions: L1 = L2, L1 < 255, L1 even
AL, AH: Block start address or erase (check) address or jump address LO or HI byte
LL, LH: Number of pure data bytes (250 max) or erase information LO or HI byte or block length of erase check (FFFFh max)
D1 … Dn: Data bytes
CKL, CKH: 16-bit checksum LO or HI byte
xx: Can be any data
–: No character (data byte) received or transmitted
ACK: The acknowledge character returned by the BSL. Can be either DATA_ACK = 90h: Frame was received correctly, command was executed successfully, or DATA_NAK = A0h: Frame not valid (for example, wrong checksum, L1 ≠ L2), command is not defined, is not allowed, or was executed unsuccessfully.
n: Number of bytes consisting of AL through Dn