SLAU358Q September 2011 – October 2019
Tx -> 3E 4E 0C 0C VL VH 08 00 D1 D2 D3 D4 D5 D6 D7 D8 CKL CKH
Rx -> ACK
Modify static levels on the I/O pins (JTAG lines).
Vcc – VCC level in mV ( VCC = VH × 256 + VL)
D1 – Open destination buffer for output and transferred data for each target
0 = none
1 = TDI (target1 to target8)
2 = TDOI (target1 to target8)
3 = TMS (target1 to target8)
4 = RST (target1 to target8)
5 = BSL-RX (target1 to target8)
D2 – data transferred to the buffer above
b0 to b7 – target1 to target8
D3 – output enable bits: 0 = high impedance, 1 = output
b2 (0x04) – common RST – the same state for all eight targets (Note: if the RST buffer above is selected, then this state is ignored)
b3 (0x08) – common TEST – the same state for all eight targets
b4 (0x10) – common TCK – the same state for all eight targets
b5 (0x20) – common TMS – the same state for all eight targets (Note: if the TMS buffer above is selected, then this state is ignored)
D4 – output level on all targets: 0 = LOW, 1 = HIGH
b2 (0x04) – common RST – the same level for all eight targets (Note: if the RST buffer above is selected, then this state is ignored)
b3 (0x08) – common TEST – the same level for all eight targets
b4 (0x10) – common TCK – the same level for all eight targets
b5 (0x20) – common TMS – the same level for all eight targets (Note: if the TMS buffer above is selected, then this state is ignored)
D5 – VCC enable bits to each targets
b0 to b7 – target1 to target8
D6 – ICC HI enable: 0 = disable, 1 = enable
D7 – spare
D8 – spare
Example 1
Generate a short RST pulse on target 1 only and force RST level LOW on targets 2 to 5 and RST level HIGH on targets 6 and 7. VCC on targets 1 to 7 is 3.3 V ( 0x0CE4) and on target 8 is 0 V (disabled).
Tx -> 3E 4E 0C 0C E4 0C 08 00 04 60 00 00 7F 00 00 00 CKL CKH
then
Tx -> 3E 4E 0C 0C E4 0C 08 00 04 61 00 00 7F 00 00 00 CKL CKH
Example 2
Generate a short RST pulse on all targets. VCC on targets 1 to 7 is 3.3 V ( 0x0CE4) and on target 8 is 0 V (disabled).
Tx -> 3E 4E 0C 0C E4 0C 08 00 00 00 04 00 7F 00 00 00 CKL CKH
then
Tx -> 3E 4E 0C 0C E4 0C 08 00 00 00 04 04 7F 00 00 00 CKL CKH