SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
22.2.7 TRIGEN Bit and SDHS_LOCK Bit
SDHSCTL3.TRIGEN has two functional roles:
- The first role is to enable the SDHS to receive the power trigger and conversion trigger signals (see Figure 22-16). SDHSCTL3.TRIGEN must be set to 1 before applying the trigger signals to the SDHS.
- The second role is to lock the SDHSCTL0, SDHSCTL1, SDHSCTL2, SDHSCTL7, SDHSWINHITH, SDHSWINLOTH, and SDHSDTCDA registers.
When SDHSCTL3.TRIGEN = 1, those registers cannot be modified. Thus, SDHSCTL3.TRIGEN must be set to 1 after updating the SDHS registers (except SDHSCTL3, SDHSCTL4, and SDHSCTL5) and before powering up the SDHS. See Section 22.2.6.1.1 for an example of the SDHS register configuration sequence. SDHSCTL3.TRIGEN can be used as the power-up trigger signal (see Figure 22-19 and Figure 22-19). However, this is not recommended when SDHSCTL0.AUTOSSDIS = 1, because the SDHS may not be fully settled before data conversion starts.
After the SDHS is triggered for power up, SDHSCTL5.SDHS_LOCK is automatically set to 1. When SDHSCTL5.SDHS_LOCK = 1, the SDHSCTL3 register is locked. Both SDHSCTL3.TRIGEN and SDHS_LOCK protect the SDHS registers from inadvertent modifications while the SDHS is active. The PGA gain registers (SDHSCTL6) are not locked even after SDHS is powered up; however, take care when updating the PGA gain while SDHS is performing data conversion. Expect a transition period before the new gain is applied (see the device-specific data sheet for the PGA gain settling time).
Table 22-5 SDHSCTL3.TRIGEN Bit and SDHSCTL5.SDHS_LOCK Bit
| Control Bit | Type | How to Set the Control Bit | Registers Locked |
|---|---|---|---|
| SDHSCTL3.TRIGEN | Read/Write | Write 1 to SDHSCTL3.TRIGEN bit | SDHSCTL0, SDHSCTL1, SDHSCTL2, SDHSCTL7, SDHSWINHITH, SDHSWINLOTH, and SDHSDTCDA |
| SDHSCTL5.SDHS_LOCK | Read Only | When SDHS_PWR_UP is asserted | SDHSCTL3 |
Table 22-6 Timing of the SDHS_LOCK bit
| Type | SDHSCTL0.TRGSRC = 0 | SDHSCTL0.TRGSRC = 1 |
|---|---|---|
| SDHS power trigger | SDHSCTL4.SDHSON = 1 (by software) | ASQ_ACQARM = 1 (from ASQ) |
| Time to set SDHS_LOCK bit after the trigger | No delay | Delay = 4 × system clock period + 4 × (PLL clock period × 10) |
To update the SDHS registers, the SDHS must be powered off first, then write 0 to SDHSCTL3.TRIGEN. When the SDHS is powered off, SDHSCTL5.SDHS_LOCK is automatically cleared to 0.
Figure 22-19 Example Using SDHSCTL3.TRIGEN Bit (SDHSCTL0.AUTOSSDIS = 0) 
Figure 22-20 Example Using SDSCTL3.TRIGEN bit (SDHSCTL0.AUTOSSDIS = 1) NOTE
In the following sections, it is assumed that SDHSCTL3.TRIGEN is set to 1 before powering up the SDHS.