SLAU472C February 2013 – November 2023 TAS2505 , TAS2505-Q1
If desired, the analog supply of AVDD could also be supplied at the same time as DVDD if the one supply is from the internal LDO or is external. This is shown in the Figure 4-2.
After RST is released (or a software reset is performed), no register writes should be performed within 1 ms.
Parameter | Minimum | Typical | Maximum | Comments |
---|---|---|---|---|
tI-S | 0 | Time between SPKVDD is provided and IOVDD is provided. | ||
tI-AD | 0 | Time between IOVDD is provided and, AVDD and DVDD are provided. | ||
tD-R | 10 ns | Time between DVDD (and IOVDD) is provided and reset can be released. | ||
tR-P | 1 ms | Time between release of the reset and when registers can be written (that is Powered up PLL and HP Level Shifters). |