SLAU472C February 2013 – November 2023 TAS2505 , TAS2505-Q1
Some specific events in the TAS2505, which may require host-processor intervention, can be used to trigger interrupts to the host processor. This avoids polling the status-flag registers continuously. The TAS2505 has two defined interrupts, INT1 and INT2, that can be configured by programming page 0, register 48 and page 0, register 49. A user can configure interrupts INT1 and INT2 to be triggered by one or many events, such as:
Each of these INT1 and INT2 interrupts can be routed to output pin GPIO. These interrupt signals can either be configured as a single pulse or a series of pulses by programming page 0, register 48, bit D0 and page 0, register 49, bit D0. If the user configures the interrupts as a series of pulses, the events trigger the start of pulses that stop when the flag registers in page 0, register 42 and page 0, register 44 are read by the user to determine the cause of the interrupt.