10.5.40 ADCCC Register (Offset = 0xFC8) [reset = 0x1]
ADC Clock Configuration (ADCCC)
The ADCCC register controls the clock source for the ADC module.
ADCCC is shown in Figure 10-54 and described in Table 10-50.
Return to Summary Table.
Figure 10-54 ADCCC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
CLKDIV |
CS |
| R-0x0 |
R/W-0x0 |
R/W-0x1 |
|
Table 10-50 ADCCC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-10 |
RESERVED |
R |
0x0 |
|
| 9-4 |
CLKDIV |
R/W |
0x0 |
PLL VCO Clock Divisor
0x0 = /1
Nh = /(N + 1)
0x1 = /2
0x2 = /3
|
| 3-0 |
CS |
R/W |
0x1 |
ADC Clock Source
0x0 = PLL VCO divided by CLKDIV
0x1 = Alternate clock source as defined by ALTCLKCFG register in System Control Module.
0x2 = MOSC
0x3 = Reserved
0x4 = Reserved
0x5 = Reserved
0x6 = Reserved
0x7 = Reserved
0x8 = Reserved
0x9 = Reserved
0xA = Reserved
0xC = Reserved
0xD = Reserved
0xE = Reserved
0xF = Reserved
|