| 31-17 |
RESERVED |
R |
0x0 |
|
| 16 |
INRDC |
R |
0x0 |
Digital Comparator Raw Interrupt Status.
0x0 = All bits in the ADCDCISC register are clear.
0x1 = At least one bit in the ADCDCISC register is set, meaning that a digital comparator interrupt has occurred.
|
| 15-12 |
RESERVED |
R |
0x0 |
|
| 11 |
DMAINR3 |
R |
0x0 |
SS3 DMA Raw Interrupt Status.
This bit is cleared by writing a 1 to the DMAINR3 bit in the ADCISC register.
0x0 = The DMA interrupt has not occurred.
0x1 = The sample sequence 3 DMA interrupt is asserted.
|
| 10 |
DMAINR2 |
R |
0x0 |
SS2 DMA Raw Interrupt Status.
This bit is cleared by writing a 1 to the DMAINR2 bit in the ADCISC register.
0x0 = The DMA interrupt has not occurred.
0x1 = The sample sequence 2 DMA interrupt is asserted.
|
| 9 |
DMAINR1 |
R |
0x0 |
SS1 DMA Raw Interrupt Status.
This bit is cleared by writing a 1 to the DMAINR1 bit in the ADCISC register.
0x0 = The DMA interrupt has not occurred.
0x1 = The sample sequence 1 DMA interrupt is asserted.
|
| 8 |
DMAINR0 |
R |
0x0 |
SS0 DMA Raw Interrupt Status.
This bit is cleared by writing a 1 to the DMAINR0 bit in the ADCISC register.
0x0 = The DMA interrupt has not occurred.
0x1 = The sample sequence 0 DMA interrupt is asserted.
|
| 7-4 |
RESERVED |
R |
0x0 |
|
| 3 |
INR3 |
R |
0x0 |
SS3 Raw Interrupt Status.
This bit is cleared by writing a 1 to the IN3 bit in the ADCISC register.
0x0 = An interrupt has not occurred.
0x1 = A sample has completed conversion and the respective ADCSSCTL3 IEn bit is set, enabling a raw interrupt.
|
| 2 |
INR2 |
R |
0x0 |
SS2 Raw Interrupt Status.
This bit is cleared by writing a 1 to the IN2 bit in the ADCISC register.
0x0 = An interrupt has not occurred.
0x1 = A sample has completed conversion and the respective ADCSSCTL2 IEn bit is set, enabling a raw interrupt.
|
| 1 |
INR1 |
R |
0x0 |
SS1 Raw Interrupt Status.
This bit is cleared by writing a 1 to the IN1 bit in the ADCISC register.
0x0 = An interrupt has not occurred.
0x1 = A sample has completed conversion and the respective ADCSSCTL1 IEn bit is set, enabling a raw interrupt.
|
| 0 |
INR0 |
R |
0x0 |
SS0 Raw Interrupt Status.
This bit is cleared by writing a 1 to the IN0 bit in the ADCISC register.
0x0 = An interrupt has not occurred.
0x1 = A sample has completed conversion and the respective ADCSSCTL0 IEn bit is set, enabling a raw interrupt.
|