SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0)
This register determines which digital comparator receives the sample from the given conversion on Sample Sequence 0, if the corresponding SnDCOP bit in the ADCSSOP0 register is set.
ADCSSDC0 is shown in Figure 10-34 and described in Table 10-27.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
S7DCSEL | S6DCSEL | S5DCSEL | S4DCSEL | ||||||||||||
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
S3DCSEL | S2DCSEL | S1DCSEL | S0DCSEL | ||||||||||||
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | ||||||||||||