SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC
This register provides a window into the sample sequencer, providing full/empty status information as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty FIFO with the head and tail pointers both pointing to index 0. The ADCSSFSTAT0 register provides status on FIFO0, which has 8 entries; ADCSSFSTAT1 on FIFO1, which has 4 entries; ADCSSFSTAT2 on FIFO2, which has 4 entries; and ADCSSFSTAT3 on FIFO3 which has a single entry.
ADCSSFSTATn is shown in Figure 10-32 and described in Table 10-25.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | FULL | RESERVED | EMPTY | ||||
| R-0x0 | R-0x0 | R-0x0 | R-0x1 | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HPTR | TPTR | ||||||
| R-0x0 | R-0x0 | ||||||