SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)
This register, along with the ADCSSEMUX3 register, defines the analog input configuration for the sample in a sequence executed with Sample Sequencer 3. If the EMUX0 bit in the ADCSSEMUX3 register is set, the MUX0 field in this register selects from AIN[23:16]. When the EMUX0 bit is clear, the MUX0 field selects from AIN[15:0]. This register is four bits wide and contains information for one possible sample. See the ADCSSMUX0 register in Section 10.5.15 for detailed bit descriptions.
ADCSSMUX3 is shown in Figure 10-43 and described in Table 10-38.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MUX0 | ||||||||||||||||||||||||||||||
| R-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||