SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Bi-SSI uses two data pins, SSInXDAT0 and SSInXDAT1, that can be configured to receive or transmit data. In Quad-SSI mode, SSInXDAT0, SSInXDAT1, SSInXDAT2 and SSInXDAT3 allow four bits of data to be received or transmitted at once. Note that in bi- and quad-SSI data transfers are only half-duplex.
By programming the MODE bits in the SSICR1 register, advanced, bi- or quad-SSI can be enabled. A direction bit, DIR, is provided to program the direction of operation during a bi- or quad-SSI transaction. Because bi- and quad-SSI cannot be full duplex, the DIR bit defines whether or not the RX FIFO is disabled. In Advanced operation, if the QSSI module TX (write) mode is enabled, the RX FIFO is automatically prevented from receiving any data. When Advanced SSI is in RX (read) mode, it operates as a full-duplex interface.
In bi- and quad-SSI mode, because only 8-bit data is allowed, the DSS bit field must be programmed to 0x7 in the SSICR0 register before transferring data to the Rx and TX FIFOs. For a data transmit, the 8-bit data packet is placed in a TX FIFO entry bits [7:0] and the mode of operation is inserted in the three most significant bits of the TX FIFO entry. The mode of operation bits [15:13] in the TX FIFO are used by the QSSI module for configuring the data on the proper pins. The following modes that may be placed on bits [15:13] of the FIFO entry are:
When data is first written to the TX FIFO, a SSInFss is asserted low indicating the start of a frame. At the EOT, bit 12 of the last data entry in the TX FIFO signifies whether a frame is ending. When the EOM bit is 1 it indicates a End of Message (EOM or STOP frame) and SSInFss is subsequently forced high. The EOM bit is cleared in the SSICR1 register on the same clock that the write to TXFIFO is completed. An EOM bit value of 0 indicates no change in transmission. If TX FIFO is emptied and SSInFSS is still asserted low, it remains low but SSInCLK is not pulsed. Likewise, if SSInFss is high when the TX FIFO is empty, it remains high.
During a Bi-SSI transmit frame, data is shifted out by two bits and placed on the corresponding two SSInDATn pins. For a quad-SSI transmit frame data is shifted out by four bits and placed on the corresponding four SSInDATn pins.
In bi-, quad- and advanced SSI, the lower byte of the Rx FIFO contains received data. The upper byte contains no valid information.
NOTE
While the master is in bi- or quad-SSI mode, if the DSS bit in the SSICR0 register is not set to 0x7, the QSSI module reverts to Legacy mode and behavior is not guaranteed.
The SSICRI1 register bits DIR and MODE are used to program what operation is needed for the next data bytes that are being loaded into the FIFO. Table 23-1 shows available modes of operation:
| DIR | MODE | Operation |
|---|---|---|
| X | 0x0 | SSI Legacy operation supporting 4 to 16 data bits |
| 0 | 0x1 | Transmit (TX) bi-SSI with 8-bits of packet data |
| 0 | 0x2 | Transmit (TX) quad-SSI with 8-bits of packet data |
| 0 | 0x3 | Transmit (TX) advanced SSI mode with 8-bits of packet data and write RX FIFO disabled |
| 1 | 0x1 | Receive (RX) bi-SSI with 8-bits of packet data |
| 1 | 0x2 | Receive (RX) quad-SSI with 8-bits of packet data |
| 1 | 0x3 | Full duplex advanced SSI with 8-bits of packet data |
NOTE
SPO = 0 and SPH = 0 is the only frame structure allowed for advanced, bi- and quad-SSI modes.
Different transactions can follow one another in the FIFOs. The following transaction combinations are allowed:
Note that switching between Quad-SSI and bi-SSI is not encouraged in a single transaction.