SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 9-21 lists the memory-mapped registers for the AES µDMA. All register offset addresses not listed in Table 9-21 should be considered as reserved locations and the register contents should not be modified.
The AES µDMA interrupt register offsets are relative to the base address 0x44030000.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x20 | AES_DMAIM | AES DMA Interrupt Mask | Section 9.6.1 |
| 0x24 | AES_DMARIS | AES DMA Raw Interrupt Status | Section 9.6.2 |
| 0x28 | AES_DMAMIS | AES DMA Masked Interrupt Status | Section 9.6.3 |
| 0x2C | AES_DMAIC | AES DMA Interrupt Clear | Section 9.6.4 |
Complex bit access types are encoded to fit into small table cells. Table 9-22 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |