SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
AES Interrupt Enable (AES_IRQENABLE)
This register contains an enable bit for each unique interrupt generated by the module. It matches the layout of AES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set to 1. An interrupt that is enabled is propagated to the NVIC controller. All AES software interrupts need to be enabled explicitly by writing this register.
NOTE
If the application uses Interrupt Mode, an interrupt is generated for each block of processed data. To support larger data flow, AES µDMA Mode should be used and the bits in the AES_IRQENABLE register should be cleared.
AES_IRQENABLE is shown in Figure 9-25 and described in Table 9-19.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CONTEXT_OUT | DATA_OUT | DATA_IN | CONTEXT_IN | |||
R-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | |||