9.5.11 AES_IRQSTATUS Register (Offset = 0x8C) [reset = 0x0]
AES Interrupt Status (AES_IRQSTATUS)
This register indicates the interrupt status. If one of the interrupt bits is set, the interrupt output is asserted.
AES_IRQSTATUS is shown in Figure 9-24 and described in Table 9-18.
Return to Summary Table.
Figure 9-24 AES_IRQSTATUS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
CONTEXT_OUT |
DATA_OUT |
DATA_IN |
CONTEXT_IN |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 9-18 AES_IRQSTATUS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-4 |
RESERVED |
R |
0x0 |
|
| 3 |
CONTEXT_OUT |
R |
0x0 |
Context Output Interrupt Status
0x0 = Authentication tag (and IV) interrupt(s) is/are not active.
0x1 = Authentication tag (and IV) interrupt(s) is/are active and the interrupt output has been triggered.
|
| 2 |
DATA_OUT |
R |
0x0 |
Data Out Interrupt Status
0x0 = The data out interrupt is not active.
0x1 = The data out interrupt is active and the interrupt output has been triggered.
|
| 1 |
DATA_IN |
R |
0x0 |
Data In Interrupt Status
0x0 = The data in interrupt is not active.
0x1 = The data in interrupt is active and the interrupt output has been triggered.
|
| 0 |
CONTEXT_IN |
R |
0x0 |
Context In Interrupt Status
0x0 = The context in interrupt is not active.
0x1 = The context in interrupt is active and the interrupt output has been triggered.
|