SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The QSSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices.
The serial bit rate is derived by dividing down the input clock (SysClk). The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register (see Section 23.5.5). The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control 0 (SSICR0) register (see Section 23.5.1).
The frequency of the output clock SSInClk is defined by:
SSInClk = SysClk / (CPSDVSR × (1 + SCR))
NOTE
SYSCLK or ALTCLK is used as the source for the SSInClk depending on how the CS field in the SSI Clock Configuration (SSICC) register is configured. For master legacy mode, the SYSCLK or ALTCLK must be at least two times faster than the SSInClk, with the restriction that SSInClk cannot be faster than 60 MHz. For slave mode, SYSCLK or ALTCLK must be at least 12 times faster than the SSInClk. In slave legacy mode, the maximum frequency of SSInClk is 10 MHz.
See the device-specific data sheet for the QSSI timing parameters.