SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The DMA attempts to execute fixed length Burst transfers if the FB bit is set in the EMACDMABUSMOD register. The maximum burst length is indicated and limited by the PBL field in the EMACDMABUSMOD register. The Receive and Transmit descriptors are always accessed in the maximum possible (limited by PBL) burst-size for the bytes to be read.
The TX DMA initiates a transfer only when there is sufficient space in the FIFO to accommodate the configured burst or remaining bytes of the end of a frame. When the DMA is configured for fixed-length burst, it transfers data using the best combination of fixed burst sizes of 4, 8, or 16 and single transactions. Otherwise when the FB bit is clear in the EMACDMABUSMOD register, the DMA transfers data as a continuous undefined burst and single transactions.
The RX DMA initiates a data transfer only when sufficient data to accommodate the configured burst is available in RX FIFO or when the end-of-frame (when it is less than the configured burst length) is detected in the RX FIFO. The DMA indicates the start address and the number of transfers required to the system. When the FB bit is set in the EMACDMABUSMOD register, then it transfers data using the best combination of fixed burst sizes of 4, 8, or 16 and single transactions. If the end-of frame is reached before the fixed-burst ends, then dummy transfers are performed in order to complete the fixed-burst. Otherwise, if the FB bit is clear, the DMA transfers data using INCR (undefined length) and SINGLE transactions. When the DMA is configured for address-aligned transfers, both DMA engines ensure that the first burst transfer on the system bus is less than or equal to the size of the configured PBL in the EMACDMABUSMOD register. Thus, all subsequent transfers start at an address that is aligned to the configured PBL. The DMA can only align the address for burst transfers up to size 16 because only bursts of 16 are supported.