SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The BUSY bit of the ADCACTSS register is used to indicate when the ADC is busy with a current conversion. When there are no triggers pending which may start a new conversion in the immediate cycle or next few cycles, the BUSY bit reads as 0. Software must read the status of the BUSY bit as clear before disabling the ADC clock by writing to the ADC Run Mode Clock Gating Control (RCGCADC) register.