11.4.1 CANCTL Register (Offset = 0x0) [reset = 0x1]
CAN Control (CANCTL)
This control register initializes the module and enables test mode and interrupts.
The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or clearing INIT. If the device goes bus-off, it sets INIT, stopping all bus activities. Once INIT has been cleared by the CPU, the device then waits for 129 occurrences of bus idle (129 * 11 consecutive high bits) before resuming normal operations. At the end of the bus-off recovery sequence, the Error Management Counters are reset.
During the waiting time after INIT is cleared, each time a sequence of 11 high bits has been monitored, a BITERROR0 code is written to the CANSTS register (the LEC field = 0x5), enabling the CPU to readily check whether the CAN bus is stuck Low or continuously disturbed, and to monitor the proceeding of the bus-off recovery sequence.
CANCTL is shown in Figure 11-5 and described in Table 11-8.
Return to Summary Table.
Figure 11-5 CANCTL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| TEST |
CCE |
DAR |
RESERVED |
EIE |
SIE |
IE |
INIT |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x1 |
|
Table 11-8 CANCTL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-8 |
RESERVED |
R |
0x0 |
|
| 7 |
TEST |
R/W |
0x0 |
Test Mode Enable.
0x0 = The CAN controller is operating normally.
0x1 = The CAN controller is in test mode.
|
| 6 |
CCE |
R/W |
0x0 |
Configuration Change Enable.
0x0 = Write accesses to the CANBIT register are not allowed.
0x1 = Write accesses to the CANBIT register are allowed if the INIT bit is 1.
|
| 5 |
DAR |
R/W |
0x0 |
Disable Automatic Retransmission.
0x0 = Auto-retransmission of disturbed messages is enabled.
0x1 = Auto-retransmission is disabled.
|
| 4 |
RESERVED |
R |
0x0 |
|
| 3 |
EIE |
R/W |
0x0 |
Error Interrupt Enable
0x0 = No error status interrupt is generated.
0x1 = A change in the BOFF or EWARN bits in the CANSTS register generates an interrupt.
|
| 2 |
SIE |
R/W |
0x0 |
Status Interrupt Enable.
0x0 = No status interrupt is generated.
0x1 = An interrupt is generated when a message has successfully been transmitted or received, or a CAN bus error has been detected. A change in the TXOK, RXOK or LEC bits in the CANSTS register generates an interrupt.
|
| 1 |
IE |
R/W |
0x0 |
CAN Interrupt Enable
0x0 = Interrupts disabled.
0x1 = Interrupts enabled.
|
| 0 |
INIT |
R/W |
0x1 |
Initialization.
0x0 = Normal operation.
0x1 = Initialization started.
|