11.4.3 CANERR Register (Offset = 0x8) [reset = 0x0]
CAN Error Counter (CANERR)
This register contains the error counter values, which can be used to analyze the cause of an error.
CANERR is shown in Figure 11-7 and described in Table 11-10.
Return to Summary Table.
Figure 11-7 CANERR Register
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
RESERVED |
R-0x0 |
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RP |
REC |
TEC |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 11-10 CANERR Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
31-16 |
RESERVED |
R |
0x0 |
|
15 |
RP |
R |
0x0 |
Received Error Passive.
0x0 = The Receive Error counter is below the Error Passive level (127 or less).
0x1 = The Receive Error counter has reached the Error Passive level (128 or greater).
|
14-8 |
REC |
R |
0x0 |
Receive Error Counter. This field contains the state of the receiver error counter (0 to 127).
|
7-0 |
TEC |
R |
0x0 |
Transmit Error Counter. This field contains the state of the transmit error counter (0 to 255).
|