SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The Run and Sleep Mode Configuration (RSCLKCFG) register provides control for the system clock in run and sleep mode. The DSCLKCFG register specifies the behavior of the clock system while in deep-sleep mode. These registers control the following clock functionality:
Providing further configuration, the PLL Frequency n (PLLFREQn) registers allow multiplication or division of the PLL VCO frequency (fVCO) by programmable values, depending on the system clock speed required.
Table 4-3 lists the state of the clock sources following a POR.
Clock Source | POR State |
---|---|
PLL | Disabled or powered off |
MOSC | Disabled or powered off |
LFIOSC | Enabled |
PIOSC | Enabled |
HIB RTCOSC | Disabled |
Figure 4-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system clock signal and can be individually enabled or disabled.
NOTE
The clock sources in Figure 4-5 include a superset of peripherals available in the family. Some peripheral clock sources may not be present on your specific device.